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Si3230
PRO SLIC (R) PR O G R A M M A B L E CMOS SLIC W I T H RI N G I N G / BA T T E R Y VO L TA G E G E N E R A T I O N
Features
Software Programmable SLIC with codec interface Software programmable internal balanced ringing up to 90 VPK (5 REN up to 4 kft, 3 REN up to 8 kft) Integrated battery supply with dynamic voltage output
On-chip dc-dc converter continuously minimizes power in all operating modes Entire solution can be powered from a single 3.3 V or 5 V supply 3.3 V to 35 V dc input range Dynamic 0 V to -94.5 V output
Software programmable signal generation and audio processing:
DTMF generation and decoding 12 kHz/16 kHz pulse metering generation Phase-continuous FSK (caller ID) generation Dual audio tone generators Smooth and abrupt polarity reversal
Ordering Information See page 103.
Extensive test and diagnostic features
Realtime dc linefeed measurement GR-909 line test capabilities
Software programmable linefeed parameters:
Ringing frequency, amplitude, cadence, and waveshape 2-wire ac impedance constant current feed (20 to 41 mA) Loop closure and ring trip thresholds and filtering
Applications
Interface to Broadcom devices
BCM11xx residential gateway BCM3341 VOIP processor BCM33xx cable modem
Voice over IP Terminal adapters Fixed cellular terminal
Description
The Si3230 is a low-voltage CMOS device that provides a multi-functional subscriber line interface ideal for customer premise equipment (CPE) applications. The ProSLIC integrates subscriber line interface circuit (SLIC) and battery generation functionality into a single CMOS integrated circuit. The integrated battery supply continuously adapts its output voltage to minimize power and enables the entire solution to be powered from a single 3.3 V (Si3230M only) or 5 V supply. The ProSLIC controls the phone line through Silicon Labs' Si3201 Linefeed IC or discrete circuitry. Si3230 features include software-configurable 5 REN internal ringing up to 90 VPK, DTMF generation and decoding, and a comprehensive set of telephony signaling capabilities for operation with only one hardware solution. The ProSLIC is packaged in a 38-pin QFN or TSSOP, and the Si3201 is packaged in a thermally-enhanced 16-pin SOIC. ProSLIC(R)
NC FSYNC RESET SDCH SDCL VDDA1 IREF CAPP QGND CAPM STIPDC SRINGDC
TEST2 PCLK INT CS SCLK SDI SDO
1 38 37 36 35 34 33 32 31 30 2 3 4 5 6 7 8 9 10 11 29 28 27 26 25 24 23 22 21 12 13 14 15 16 17 18 19 20
SPI control interface Extensive programmable interrupts 100% software configurable global solution Lead-Free and RoHS-compliant package options available
Pin Assignments QFN Package
SDITHRU DCDRV DCFF TEST1 GNDD VDDD ITIPN ITIPP VDDA2 IRINGP IRINGN IGMP
Patents pending U.S. Patent #6,567,521 U.S. Patent #6,812,744 Other patents pending
Functional Block Diagram
INT RESET SPI Control Interface CS SCLK SDO SDI
Si3230
Ringing Generator Loop Closure Detect Ring Trip Detect Line Diagnostics SLIC Linefeed Control Linefeed Interface Tip Ring
Tone Generators FSK Caller ID Pulse Metering Impedance Synth
DTMF Decoder PLL FSYNC PCLK
Linefeed Monitor
DC-DC Converter Controller
Battery
Preliminary Rev. 0.96 7/05
Copyright (c) 2005 by Silicon Laboratories
STIPE SVBAT SRINGE STIPAC SRINGAC IGMN GNDA
Si3230
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si3230
2
Preliminary Rev. 0.96
Si3230 TABLE O F CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1. Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2. Battery Voltage Generation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3. Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.5. Pulse Metering Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.7. Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.8. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.9. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.10. Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4. Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 4.1. DTMF Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 4.2. Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.3. Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.4. SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.5. FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 5. Pin Descriptions: Si3230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7. Ordering Guide1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8. Package Outline: 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9. Package Outline: 38-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Preliminary Rev. 0.96
3
Si3230
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information1
Parameter DC Supply Voltage Input Current, Digital Input Pins Digital Input Voltage ESD, Human Body Model Operating Temperature Range Storage Temperature Range TSSOP-38 Thermal Resistance, Typical QFN-38 Thermal Resistance, Typical Continuous Power Dissipation DC Supply Voltage Battery Supply Voltage Input Voltage: TIP, RING, SRINGE, STIPE pins Input Voltage: ITIPP, ITIPN, IRINGP, IRINGN pins Operating Temperature Range Storage Temperature Range SOIC-16 Thermal Resistance, Typical Continuous Power Dissipation2
3 2 2 2
Symbol Si3230 VDDD, VDDA1, VDDA2 IIN VIND TA TSTG JA JA PD Si3201 VDD VBAT VINHV VIN TA TSTG JA PD
Value -0.5 to 6.0 10 -0.3 to (VDDD + 0.3) 2000 -40 to 100 -40 to 150 70 35 0.7 -0.5 to 6.0 -104 (VBAT - 0.3) to (VDD + 0.3) -0.3 to (VDD + 0.3) -40 to 100 -40 to 150 55 1.0
Unit V mA V V C C C/W C/W W V V V V C C C/W W
Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Operation above 125 oC junction temperature may degrade device reliability. 3. Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad.
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Preliminary Rev. 0.96
Si3230
Table 2. Recommended Operating Conditions
Parameter Ambient Temperature Ambient Temperature Si3230 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage Symbol TA TA VDDD,VDDA1 ,VDDA2 VDD VBAT VBATH = VBAT Test Condition K-grade B-grade Min* 0 -40 3.13 3.13 -96 Typ 25 25 3.3/5.0 3.3/5.0 -- Max* 70 85 5.25 5.0 0 Unit
oC o
C
V V V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 oC unless otherwise stated. Product specifications are only guaranteed when the typical application circuit (including component tolerances) is used.
Table 3. AC Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade)
Parameter Overload Level Audio Tone Generator Signal-to-Distortion Ratio1 Intermodulation Distortion 2-Wire Return Loss Idle Channel Noise
3
Test Condition TX/RX Performance THD = 1.5% 0 dBm0, Active off-hook, and OHT, any Zac 200 Hz to 3.4 kHz Noise Performance C-Message Weighted Psophometric Weighted 3 kHz flat
Min 2.5 45 -- 30 -- -- -- 40 40 40
Typ -- -- -- 35 -- -- -- -- -- --
Max -- -- -45 -- 15 -75 18 -- -- --
Unit VPK dB dB dB dBrnC dBmP dBrn dB dB dB
PSRR from VDDA PSRR from VDDD PSRR from VBAT
RX and TX, DC to 3.4 kHz RX and TX, DC to 3.4 kHz RX and TX, DC to 3.4 kHz
Notes: 1. Analog signal measured as VTIP - VRING. Assumes ideal line impedance matching. 2. The quantization errors inherent in the /A-law companding process can generate slightly worse gain tracking performance in the signal range of 3 dB to -37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate. 3. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed -55 dBm. 4. Assumes normal distribution of betas.
Preliminary Rev. 0.96
5
Si3230
Table 3. AC Characteristics (Continued)
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade)
Parameter Longitudinal to Metallic Balance
Test Condition Longitudinal Performance 200 Hz to 3.4 kHz, Q1,Q2 150, 1% mismatch Q1,Q2 = 60 to 2404 Q1,Q2 = 300 to 800 Using Si3201
4
Min 56 43 53 TBD 40
Typ 60 60 60 60 --
Max -- -- -- -- --
Unit dB dB dB dB dB
Metallic to Longitudinal Balance Longitudinal Impedance
200 Hz to 3.4 kHz 200 Hz to 3.4 kHz at TIP or RING Register selectable
ETBO/ETBA
00 01 10 Longitudinal Current per Pin Active off-hook 200 Hz to 3.4 kHz Register selectable
ETBO/ETBA
-- -- --
33 17 17
-- -- --

00 01 10
-- -- --
4 8 8
-- -- --
mA mA mA
Notes: 1. Analog signal measured as VTIP - VRING. Assumes ideal line impedance matching. 2. The quantization errors inherent in the /A-law companding process can generate slightly worse gain tracking performance in the signal range of 3 dB to -37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate. 3. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed -55 dBm. 4. Assumes normal distribution of betas.
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Preliminary Rev. 0.96
Si3230
9 8 7 6
Fundamental Output Power 5 (dBm0) Acceptable Region
4 3
2.6
2 1 0 1 2 3 4 5 6 7 8 9
Fundamental Input Power (dBm0)
Figure 1. Overload Compression Performance Table 4. Linefeed Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade)
Parameter Loop Resistance Range DC Loop Current Accuracy DC Open Circuit Voltage Accuracy DC Differential Output Resistance DC Open Circuit Voltage-- Ground Start DC Output Resistance-- Ground Start DC Output Resistance-- Ground Start Loop Closure/Ring Ground Detect Threshold Accuracy Ring Trip Threshold Accuracy Ring Trip Response Time Ring Amplitude Ring DC Offset
Symbol RLOOP
Test Condition See note.* ILIM = 29 mA, ETBA = 4 mA Active Mode; VOC = 48 V, VTIP - VRING
Min 0 -10 -4 -- -4 -- 150 -20 -10 -- 44 0
Typ -- -- -- 160 -- 160 -- -- -- -- -- --
Max 160 10 4 -- 4 -- -- 20 10 -- -- --
Unit % V V k % %
RDO VOCTO RROTO RTOTO
ILOOP < ILIM IRINGVTR ROS
5 REN load; sine wave; RLOOP = 160 , VBAT = -75 V Programmable in Indirect Register 19
Vrms V
Preliminary Rev. 0.96
7
Si3230
Table 4. Linefeed Characteristics (Continued)
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade)
Parameter Trapezoidal Ring Crest Factor Accuracy Sinusoidal Ring Crest Factor Ringing Frequency Accuracy Ringing Cadence Accuracy Calibration Time Power Alarm Threshold Accuracy
Symbol
Test Condition Crest factor = 1.3
Min -.05 1.35
Typ -- -- -- -- -- --
Max .05 1.45 1 50 600 25
Unit
RCF f = 20 Hz Accuracy of ON/OFF Times CAL to CAL Bit At Power Threshold = 300 mW
-1 -50 -- -25
% ms ms %
*Note: DC resistance round trip; 160 corresponds to 2 kft 26 gauge AWG.
Table 5. Monitor ADC Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade)
Parameter Differential Nonlinearity (6-bit resolution) Integral Nonlinearity (6-bit resolution) Gain Error (voltage) Gain Error (current)
Symbol DNLE INLE
Test Condition
Min -1/2 -1 -- --
Typ -- -- -- --
Max 1/2 1 10 20
Unit LSB LSB % %
Table 6. Si3230 DC Characteristics, VDDA = VDDD = 5.0 V
(VDDA,VDDD = 4.75 V to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage
Symbol VIH VIL VOH
Test Condition
Min 0.7 x VDDD --
Typ -- -- -- -- --
Max -- 0.3 x VDD
D
Unit V V V V V
DIO1,DIO2,SDITHRU:IO = -4 mA VDDD - 0.6 SDO:IO = -8 mA DOUT: IO = -40 mA
-- -- 0.4
VDDD - 0.8 --
Low Level Output Voltage
VOL
DIO1,DIO2,DOUT,SDITHRU: IO = 4 mA SDO,INT:IO = 8 mA
Input Leakage Current
IL
-10
--
10
A
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Preliminary Rev. 0.96
Si3230
Table 7. Si3230 DC Characteristics, VDDA = VDDD = 3.3 V
(VDDA,VDDD = 3.13 V to 3.47 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage
Symbol VIH VIL VOH
Test Condition
Min 0.7 x VDDD --
Typ -- -- -- -- --
Max -- 0.3 x VDD
D
Unit V V V V V
DIO1,DIO2,SDITHRU:IO = -2 mA VDDD - 0.6 SDO:IO = -4 mA DOUT: IO = -40 mA
-- -- 0.4
VDDD - 0.8 --
Low Level Output Voltage
VOL
DIO1,DIO2,DOUT,SDITHRU: IO = 2 mA SDO,INT:IO = 4 mA
Input Leakage Current
IL
-10
--
10
A
Table 8. Power Supply Characteristics
(VDDA,VDDD = 3.13 V to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade)
Parameter Power Supply Current, Analog and Digital
Symbol IA + ID
Test Condition Sleep (RESET = 0) Open Active on-hook ETBO = 4 mA, codec and Gm amplifier powered down Active OHT ETBO = 4 mA Active off-hook ETBA = 4 mA, ILIM = 20 mA Ground-start Ringing Sinewave, REN = 1, VPK = 56 V
Typ1 0.1 33 37
Typ2 0.13 42.8 53
Max 0.2 49 68
Unit mA mA mA
57 73 36 45 -- -- -- -- --
72 88 47 55 100 100 110 1 1
83 99 55 65 -- -- -- -- --
mA mA mA mA A A A mA mA
VDD Supply Current (Si3201)
IVDD
Sleep mode, RESET = 0 Open (high impedance) Active on-hook standby Forward/reverse active off-hook, no ILOOP, ETBO = 4 mA, VBAT = -24 V Forward/reverse OHT, ETBO = 4 mA, VBAT = -70 V
Preliminary Rev. 0.96
9
Si3230
Table 8. Power Supply Characteristics (Continued)
(VDDA,VDDD = 3.13 V to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade)
Parameter VBAT Supply Current3
Symbol IBAT
Test Condition Sleep (RESET = 0) Open (DCOF = 1) Active on-hook VOC = 48 V, ETBO = 4 mA Active OHT ETBO = 4 mA Active off-hook ETBA = 4 mA, ILIM = 20 mA Ground-start Ringing VPK_RING = 56 VPK, sinewave ringing, REN = 1
Typ1 -- -- -- -- -- -- --
Typ2 0 0 3 11 30 2 5.5
Max -- -- -- -- -- -- --
Unit mA mA mA mA mA mA mA
Notes: 1. VDDD, VDDA = 3.3 V. 2. VDDD, VDDA = 5.25 V. 3. IBAT = current from VBAT (the large negative supply). For a switched-mode power supply regulator efficiency of 71%, the user can calculate the regulator current consumption as IBAT VBAT/(0.71 VDC).
Table 9. Switching Characteristics--General Inputs
VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade, CL = 20 pF)
Parameter Rise Time, RESET RESET Pulse Width
Symbol tr trl
Min -- 100
Typ -- --
Max 20 --
Unit ns ns
Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VD - 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
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Preliminary Rev. 0.96
Si3230
Table 10. Switching Characteristics--SPI
VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade, CL = 20 pF
Parameter Cycle Time SCLK Rise Time, SCLK Fall Time, SCLK Delay Time, SCLK Fall to SDO Active Delay Time, SCLK Fall to SDO Transition Delay Time, CS Rise to SDO Tri-state Setup Time, CS to SCLK Fall Hold Time, CS to SCLK Rise Setup Time, SDI to SCLK Rise Hold Time, SDI to SCLK Rise Delay Time between Chip Selects (Continuous SCLK) Delay Time between Chip Selects (Non-continuous SCLK) SDI to SDITHRU Propagation Delay
Symbol tc tr tf td1 td2 td3 tsu1 th1 tsu2 th2 tcs tcs td4
Test Conditions
Min 0.062 -- -- -- -- -- 25 20 25 20 440 220 --
Typ -- -- -- -- -- -- -- -- -- -- -- -- 4
Max -- 25 25 20 20 20 -- -- -- -- -- -- 10
Unit sec ns ns ns ns ns ns ns ns ns ns ns ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDD -0.4 V, VIL = 0.4 V
tr
tthru tc
tr
SCLK
tsu1
th1 tcs tsu2 th2
CS
SDI
td1 td2 td3
SDO
Figure 2. SPI Timing Diagram
Preliminary Rev. 0.96
11
Si3230
VCC
32
GNDD 31
23
10
27
TEST2 4
GNDA
VDDA1
R1 200k 15 C24 0.1uF 20 C3 220nF R8 470
VDDA2
VDDD 30
TEST
STIPDC STIPAC
SCLK SDI SDO CS
38 37 36 1 6 3
VCC
SPI Bus
8
GND 7
C18 4.7F
C19 4.7F
FSYNC PCLK ITIPN IRINGN ITIPP IRINGP STIPE SRINGE
Clock Inputs
VCC
2 R32 10k
VDD
To codec
ITIPN IRINGN
4.7F C5 22nF C6 22nF 3 1
13 16 14 11 10 R7 4.02k R2 196k
25 28 26 17 R4 196k 19 R6 4.02k 18 R5 200k C4 220nF R9 470
Protection Circuit
Si3201
TIP
TIP
ITIPP IRINGP STIPE SRINGE
Si3230/Si3230M
15
29
INT RESET
2 7 Note 2 R26 2 40.2k
To codec
RING
RING
VBATH
VBAT
SVBAT
IGMP IGMN IREF
24 22 11 12 14 C2 10uF C1 10uF R14 40.2k
To codec
5
4
21 16
SRINGAC DCDRV SRINGDC SDCH SDCL
CAPP CAPM DCFF QGND
Notes: 1. Values and configurations for these components can be derived from Table 16 or from App Note 45. 2. Only one component per system needed. 3. All circuit ground should have a singlepoint connection to the ground plane .
R3 200k C26 0.1uF R21 15
1 R29
13
34
SDCH
1 R28
DCFF
SDCL
VCC
DCDRV
Q9 2N2222
33
9
8
GND
VDDA1 C15 0.1uF
VDDA2 C16 C17 0.1uF 0.1uF
VDDD C30 10uF
VDC
Note 1
VBAT
DC-DC Converter VDC Circuit
Figure 3. Si3230/Si3230M Application Circuit Using Si3201 Table 11. Si3230/Si3230M + Si3201 External Component Values
Component (s)
C1,C2 C3,C4 C5,C6 C15,C16,C17,C24 C18,C19 C26 C30 R1,R3,R5 R2,R4 R6,R7 R8,R9 R14,R26* R15 R21 R28,R29 R32* Q9
Value
10 F, 6 V Ceramic or 16 V Low Leakage Electrolytic, 20% 220 nF, 100 V, X7R, 20% 22 nF, 100 V, X7R, 20% 0.1 F, 6 V, Y5V, 20% 4.7 F, Cer. 6 V, X7R, 20% 0.1 F, 100 V, X7R, 20% 10 F, 6 V, Electrolytic, 20% 200 k, 1/10 W, 1% 196 k, 1/10 W, 1% 4.02 k, 1/10 W, 1% 470 , 1/10 W, 1% 40.2 k, 1/10 W, 1% 243 , 1/10 W, 1% 15 , 1/4 W, 5% 1/10 W, 1% (See AN45 or Table 16 for value selection) 10 k, 1/10 W, 5% 60 V, General Purpose Switching NPN
Supplier
Murata, Nichicon URL1C100MD Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Panasonic
ON Semi MMBT2222ALT1; Central Semi CMPT2222A; Zetex FMMT2222
*Note: Only one component per system needed.
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Preliminary Rev. 0.96
Si3230
VDC F1
SDCH R19 1
Note 1
SDCL R201
R181
C25 2 10uF
C14 2 0.1uF
Si3230
C10 0.1 F
R16 200 Q7 FZT953
DCFF
Q8 2N2222
D1 ES1D C9 10uF
VBAT
R17 L1 DCDRV
Note 1
GND
Notes: 1. Values and configurations for these components can be derived from Table 17 or from App Note 45. 2. Voltage rating for C14 and C25 must be greater than VDC.
Figure 4. Si3230 DC-DC Converter Circuit Table 12. Si3230 DC-DC Converter Component Values
Component (s) C9 C10 C14* C25* R16 R17 R18 R19,R20 F1 D1 L1 Value 10 F, 100 V, Electrolytic, 20% 0.1 F, 50 V, X7R, 20% 0.1 F, X7R, 20% 10 F, Electrolytic, 20% 200 , 1/10 W, 5% 1/10 W, 5% (See AN45 or Table 17 for value selection) 1/4 W, 5% (See AN45 or Table 17 for value selection) 1/10 W, 1% (See AN45 or Table 17 for value selection) Fuse Ultra Fast Recovery 200 V, 1A Rectifier 1A, Shielded Inductor (See AN45 or Table 17 for value selection) 120 V, High Current Switching PNP 60 V, General Purpose Switching NPN Belfuse SSQ Series General Semi ES1D; Central Semi CMR1U-02 API Delevan SPD127 series, Sumida CDRH127 series, Datatronics DR340-1 series, Coilcraft DS5022 Zetex FZT953, FZT955, ZTX953, ZTX955 ON Semi MMBT2222ALT1, MPS2222A; Central Semi CMPT2222A; Zetex FMMT2222 Supplier Panasonic Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Panasonic
Q7 Q8
*Note: Voltage rating of this device must be greater than VDC.
Preliminary Rev. 0.96
13
Si3230
VDC
F1
SDCH R191
Note 1 R181
SDCL R201
C252 10F
C142 0.1F
Si3230M
1 C27 470pF DCFF M1 IRLL014N R22 22 2 3 4 6 10
D1 ES1D C9 10F
VBAT
T1 1
Note 1
R17 200k DCDRV NC
Notes: 1. Values and configurations for these components can be derived from Table 18 or from App Note 45. 2. Voltage rating for C14 and C25 must be greater than VDC.
GND
Figure 5. Si3230M MOSFET/Transformer DC-DC Converter Circuit
Table 13. Si3230M MOSFET/Transformer DC-DC Converter Component Values
Component(s) C9 C14* C25* C27 R17 R18 R19,R20 R22 F1 D1 T1 Value 10 F, 100 V, Electrolytic, 20% 0.1 F, X7R, 20% 10 F, Electrolytic, 20% 470 pF, 100 V, X7R, 20% 200 k, 1/10 W, 5% 1/4 W, 5% (See AN45 or Table 21 for value selection) 1/10 W, 1% (See AN45 or Table 21 for value selection) 22 , 1/10 W, 5% Fuse Ultra Fast Recovery 200 V, 1A Rectifier Power Transformer Belfuse SSQ Series General Semi ES1D; Central Semi CMR1U-02 Coiltronic CTX01-15275; Datatronics SM76315; Midcom 31353R-02 Intl Rect. IRLL014N; Intersil HUF76609D3S; ST Micro STD5NE10L, STN2NE10L Supplier Panasonic Murata, Johanson, Novacap, Venkel Panasonic Murata, Johanson, Novacap, Venkel
M1
100 V, Logic Level Input MOSFET
*Note: Voltage rating of this device must be greater than VDC.
14
Preliminary Rev. 0.96
Si3230
VCC
32
31
23
10
27
TEST2
TEST1
GNDA
VDDA1
VDDA2
GNDD
R1 200k GND 15 20 C3 220nF R8 470
VDDD
30
4
GND
SCLK STIPDC STIPAC SDI SDO CS FSYNC PCLK
38 37 36 1 6 3
SPI Bus Clock Inputs
VCC R32 2 10k
Q1 5401 To codec
TIP
Protection Circuit
25 28 R2 200k 26 Q2 5401 Q5 5551 Q3 5401 17 R4 200k 19
Q6 5551 C5 22nF C6 22nF
IRINGN STIPE
C8 220nF R6 80.6
R13 5.1k
Si3230/Si3230M
R10 10
Q4 5401
29
ITIPP
INT RESET
2 7 Note 2 R26 2 40.2k
RING
To codec
IRINGP ITIPN SRINGE
R11 10 C7 220nF R7 80.6
R12 5.1k
R5 200k
18
SVBAT
IGMP
24
IGMN 22 IREF
11 12 14 C2 10uF
To codec
C4 220nF
R9 470
21 16
Notes: 1. Values and configurations for these components can be derived from Table 16 or from App Note 45. 2. Only one component per system needed. 3. All circuit ground should have a single-point connection to the ground plane.
R21 15 C26 0.1uF Q9 2N2222 VCC R29 1 R28 1 R3 200k
SRINGAC SRINGDC DCDRV SDCH DCFF SDCL
CAPP CAPM QGND
C1 10uF
R14 40.2k
GND
13
9
8
34
33
DCDRV
SDCH
DCFF
SDCL
VDC
VDDA1 C15 0.1uF C16 0.1uF
VDDA2 C17 0.1uF
VDDD C30 10uF
Note 1
VBAT
DC-DC Converter Circuit
VDC
Figure 6. Si3230/Si3230M Typical Application Circuit Using Discrete Components Table 14. Si3230/Si3230M External Component Values--Discrete Solution
Component
C1,C2 C3,C4 C5,C6 C7,C8 C15,C16,C17 C26 C30 Q1,Q2,Q3,Q4 Q5,Q6 Q9
Value
10 F, 6 V Ceramic or 16 V Low Leakage Electrolytic, 20% 220 nF, 100 V, X7R, 20% 22 nF, 100 V, X7R, 20% 220 nF, 50 V, X7R, 20% 0.1 F, 6 V, Y5V, 20% 0.1 F, 100 V, X7R, 20% 10 F, 16 V, Electrolytic, 20% 120 V, PNP, BJT 120 V, NPN, BJT NPN General Purpose BJT
Supplier/Part Number
Murata, Panasonic, Nichicon URL1C100MD Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Panasonic Central Semi CMPT5401; ON Semi MMBT5401LT1, 2N5401; Zetex FMMT5401 Central Semi CZT5551, ON Semi 2N5551 ON Semi MMBT2222ALT1, MPS2222A; Central Semi CMPT2222A; Zetex FMMT2222
R1,R2,R3,R4,R5 200 k, 1/10 W, 1% R6,R7 80.6 , 1/4 W, 1% R8,R9 470 , 1/10 W, 1% R10,R11 10 , 1/10 W, 5% R12,R13 5.1 k, 1/10 W, 5% R14,R26* 40.2 k, 1/10 W, 1% R15 243 , 1/10 W, 1% R21 15 , 1/4 W, 1% R28,R29 1/10 W, 1% (See AN45 or Table 16 for value selection) R32* 10 k, 1/10 W, 5% *Note: Only one component per system needed.
Preliminary Rev. 0.96
15
Si3230
R8 20k
VINp
To TIP
R10 39.2k C5 0.1 F
TX gain = 0.6622
CMlevel
R11 39.2k
VINm
R9 20k
To RING
C6 0.1F VCC 10 U1 8 LMV358
BCM11xx
VDDA1
2 R6 10k R5 20k R7 10k
R1 121
IGMN
VOUTp
5
RX gain = 1.2346
Figure 7. Interface to Broadcom BCM11xx Table 15. External Component Values--BCM11xx Interface
Component C1 C5, C6 R1, R2 R5, R8, R9 R6, R7 R10, R11 U1 Value 0.1 F, 6 V, Y5V, 20% 0.1 F, 100 V, X7R, 20% 121 , 1/10 W, 1% 20 k, 1/10 W, 1% 10 k, 1/10 W, 1% 39.2 k, 1/10 W, 1% Dual Rail-to-Rail Op Amp Texas Instruments LMV358, Micrel MIC7122 Comments/Part Number Murata, Johnson, Novacap, Venkel Murata, Johnson, Novacap, Venkel
16
Preliminary Rev. 0.96
+ -
6
7
R2 121
24
IGMP
VCC 4 C1 0.1F 23 Opamp decoupling
GNDA
Si3230/Si3230M
VOUTm
3
+ -
1
22
Si3230
Table 16. Component Value Selection for Si3230
Component R28 Value 1/10 W, 1% resistor For VDD = 3.3 V: 26.1 k For VDD = 5.0 V: 37.4 k 1/10 W, 1% resistor For VCLAMP = 80 V: 541 k For VCLAMP = 85 V: 574 k For VCLAMP = 100 V: 676 k Comments R28 = (VDD + VBE)/148 A where VBE is the nominal VBE for Q9 R29 = VCLAMP/148 A where VCLAMP is the clamping voltage for VBAT
R29
Table 17. Component Value Selection Examples for DC-DC Converter
VDC 5V 12 V 24 V Maximum Ringing Load/Loop Resistance 3 REN/117 5 REN/117 5 REN/117 L1 33 H 150 H 560 H R17 100 162 274 R18 0.12 0.56 2.2 R19, R20 16.5 k 56.2k 121 k
Note: There are other system and software conditions that influence component value selection. Please refer to "AN45: "Design Guide for the Si3210/15/16 DC-DC Converter" for detailed guidance.
Table 18. Component Value Selection Examples for Si3230M MOSFET/Transformer DC-DC Converter
VDC 3.3 V 5.0 V 12 V 24 Maximum Ringing Load/Loop Resistance 3 REN/117 5 REN/117 5 REN/117 5 REN/117 Transformer Ratio 1:2 1:2 1:3 1:4 R18 0.06 0.10 0.6 2.1 R19, R20 7.15 16.5 56.2 121
Note: There are other system and software conditions that influence component value selection. Please refer to "AN45: "Design Guide for the Si3210/15/16 DC-DC Converter" for detailed guidance.
Preliminary Rev. 0.96
17
Si3230
2. Functional Description
The Si3230 ProSLIC(R) is a single low-voltage CMOS device that provides all the SLIC, DTMF detection, and signal generation functions needed for a complete analog telephone interface when connected to an external codec. The ProSLIC performs all battery, overvoltage, ringing, supervision, and test functions. Unlike most monolithic SLICs, the Si3230 does not require externally supplied high-voltage battery supplies. Instead, it generates all necessary battery voltages from a positive dc supply using its own dc-dc converter controller. Two fully programmable tone generators can produce DTMF tones, phase continuous FSK (caller ID) signaling, and call progress tones. DTMF decoding and pulse metering signal generation are also integrated. The Si3201 linefeed interface IC performs all high voltage functions. As an option, the Si3201 can also be replaced with low-cost discrete components as shown in the typical application circuit in Figure 6. The 3230 is primarily meant to be used with Broadcom devices BCM1101, BCM3351/52, and BCM6352. Special directions for interfacing and operating the Si3230 are needed. Please contact Silicon Laboratories for guidance with other applications. The linefeed provides programmable on-hook voltage, programmable off-hook loop current, reverse battery operation, loop or ground start operation, and on-hook transmission ringing voltage. Loop current and voltage are continuously monitored using an integrated A/D converter. Balanced 5 REN ringing with or without a programmable dc offset is integrated. The available offset, frequency, waveshape, and cadence options are designed to ring the widest variety of terminal devices and to reduce external controller requirements.
V (TIP-RING ) (V) Constant Voltage Zone
VOC
R O =160 I LIM
Constant Current Zone I LO O P (m A)
Figure 8. Simplified DC Current/Voltage Linefeed Characteristic
The TIP-to-RING voltage (VOC) is offset from ground by a programmable voltage (VCM) to provide voltage headroom to the positive-most terminal (TIP in forward polarity states and RING in reverse polarity states) for carrying audio signals. Table 19 summarizes the parameters to be initialized before entering an active state.
Table 19. Programmable Ranges of DC Linefeed Characteristics
Parameter ILIM VOC VCM Programmable Range 20 to 41 mA 0 to 94.5 V 0 to 94.5 V Default Value 20 mA 48 V 3V Register Bits ILIM[2:0] VOC[5:0] VCM[5:0] Location* Direct Register 71 Direct Register 72 Direct Register 73
2.1. Linefeed Interface
The ProSLIC's linefeed interface offers a rich set of features and programmable flexibility to meet the broadest applications requirements. The dc linefeed characteristics are software programmable; key current, voltage, and power measurements are acquired in realtime and provided in software registers. 2.1.1. DC Feed Characteristics The ProSLIC has programmable constant voltage and constant current zones as depicted in Figure 8. Open circuit TIP-to-RING voltage (VOC) defines the constant voltage zone and is programmable from 0 V to 94.5 V in 1.5 V steps. The loop current limit (ILIM) defines the constant current zone and is programmable from 20 mA to 41 mA in 3 mA steps. The ProSLIC has an inherent dc output resistance (RO) of 160 .
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly.
2.1.2. Linefeed Architecture The ProSLIC is a low-voltage CMOS device that uses either an Si3201 linefeed interface IC or low-cost external components to control the high voltages required for subscriber line interfaces. The ProSLIC uses both voltage and current sensing to control TIP and RING. DC and AC line voltages on TIP and RING are measured through sense resistors RDC and RAC, respectively. The ProSLIC uses linefeed transistors QP and QN to drive TIP and RING. QDN isolates the high-voltage base of QN from the ProSLIC. The ProSLIC measures voltage at various nodes in
18
Preliminary Rev. 0.96
Si3230
order to monitor the linefeed current. RDC, RSE, and RBAT provide access to these measuring points. The sense circuitry is calibrated on-chip to guarantee measurement accuracy with standard external component tolerances. See "2.1.9. Linefeed Calibration" on page 23 for details. 2.1.3. Linefeed Operation States The ProSLIC linefeed has eight states of operation as shown in Table 20. The state of operation is controlled using the Linefeed Control register (direct Register 64). The open state turns off all currents into the external bipolar transistors and can be used in the presence of fault conditions on the line and to generate Open Switch Intervals (OSIs). TIP and RING are effectively tri-stated with a dc output impedance of about 150 k. The ProSLIC can also automatically enter the open state if it detects excessive power being consumed in the external bipolar transistors. See "2.1.5. Power Monitoring and Line Fault Detection" on page 20 for more details. In the forward active and reverse active states, linefeed circuitry is on and the audio signal paths are powered down. In the forward and reverse on-hook transmission states audio signal paths are powered up to provide data transmission during an on-hook loop condition. LF[2:0]* 000 001 010 011 100 101 110 111 Linefeed State Open Forward Active Forward On-Hook Transmission TIP Open Ringing Reverse Active Reverse On-Hook Transmission Ring Open The TIP Open state turns off all control currents to the external bipolar devices connected to TIP and provides an active linefeed on RING for ground start operation. The RING Open state provides similar operation with the RING drivers off and TIP active. The ringing state drives waveforms onto the line. programmable ringing
2.1.4. Loop Voltage and Current Monitoring The ProSLIC continuously monitors the TIP and RING voltages and external BJT currents. These values are available in registers 78-89. Table 21 on page 20 lists the values that are measured and their associated registers. An internal A/D converter samples the measured voltages and currents from the analog sense circuitry and translates them into the digital domain. The A/D updates the samples at an 800 Hz rate. Two derived values are also reported--loop voltage and loop current. The loop voltage, VTIP - VRING, is reported as a 1-bit sign, 6-bit magnitude format. For ground start operation the reported value is the RING voltage. The loop current, (IQ1 - IQ2 + IQ5 -IQ6)/2, is reported in a 1bit sign, 6-bit magnitude format. In RING open and TIP open states the loop current is reported as (IQ1 - IQ2) + (IQ5 -IQ6).
Table 20. ProSLIC Linefeed Operations
Description TIP and RING tri-stated. VTIP > VRING. VTIP > VRING; audio signal paths powered on. TIP tri-stated, RING active; used for ground start. Ringing waveform applied to TIP and RING. VRING > VTIP. VRING > VTIP; audio signal paths powered on. RING tri-stated, TIP active.
Note: The Linefeed register (LF) is located in direct Register 64.
Preliminary Rev. 0.96
19
Si3230
Table 21. Measured Realtime Linefeed Interface Characteristics
Parameter Loop Voltage Sense (VTIP - VRING) Loop Current Sense TIP Voltage Sense RING Voltage Sense Battery Voltage Sense 1 (VBAT) Battery Voltage Sense 2 (VBAT) Transistor 1 Current Sense Transistor 2 Current Sense Transistor 3 Current Sense Transistor 4 Current Sense Transistor 5 Current Sense Transistor 6 Current Sense Measurement Range -94.5 to +94.5 V -78.75 to +78.5 mA 0 to -95.88 V 0 to -95.88 V 0 to -95.88 V 0 to -95.88 V 0 to 81.35 mA 0 to 81.35 mA 0 to 9.59 mA 0 to 9.59 mA 0 to 80.58 mA 0 to 80.58 mA Resolution 1.5 V 1.25 mA 0.376 V 0.376 V 0.376 V 0.376 V 0.319 mA 0.319 mA 37.6 A 37.6 A 0.316 mA 0.316 mA Register Bits LVSP, LVS[6:0] LCSP, LCS[5:0] VTIP[7:0] VRING[7:0] VBATS1[7:0] VBATS2[7:0] IQ1[7:0] IQ2[7:0] IQ3[7:0] IQ4[7:0] IQ5[7:0] IQ6[7:0] Location* Direct Register 78 Direct Register 79 Direct Register 80 Direct Register 81 Direct Register 82 Direct Register 83 Direct Register 84 Direct Register 85 Direct Register 86 Direct Register 87 Direct Register 88 Direct Register 89
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly.
2.1.5. Power Monitoring and Line Fault Detection In addition to reporting voltages and currents, the ProSLIC continuously monitors the power dissipated in each external bipolar transistor. Realtime output power of any one of the six linefeed transistors can be read by setting the Power Monitor Pointer (direct Register 76) to point to the desired transistor and then reading the Line Power Output Monitor (direct Register 77). The realtime power measurements are low-pass filtered and compared to a maximum power threshold. Maximum power thresholds and filter time constants are software programmable and should be set for each transistor pair based on the characteristics of the transistors used. Table 22 describes the registers associated with this function. If the power in any external transistor exceeds the programmed threshold, a power alarm event is triggered. The ProSLIC sets the Power Alarm register bit, generates an interrupt (if enabled), and automatically enters the Open state (if AOPN = 1). This feature protects the external transistors from fault conditions and, combined with the loop voltage and current monitors, allows diagnosis of
the type of fault condition present on the line. The value of each thermal low-pass filter pole is set according to the equation:
4096 3 thermal LPF register = ------------------ x 2 800 x
where is the thermal time constant of the transistor package, 4096 is the full range of the 12-bit register, and 800 is the sample rate in hertz. Generally = 3 seconds for SOT223 packages and = 0.16 seconds for SOT23, but check with the manufacturer for the package thermal constant of a specific device. For example, the power alarm threshold and low-pass filter values for Q5 and Q6 using a SOT223 package transistor are computed as follows:
P MAX 7 1.28 7 PT56 = ------------------------------ x 2 = ----------------- x 2 = 5389 = 150D Resolution 0.0304
Thus, indirect Register 34 should be set to 150Dh.
Note: The power monitor resolution for Q3 and Q4 is different from that of Q1, Q2, Q5, and Q6.
20
Preliminary Rev. 0.96
Si3230
Table 22. Associated Power Monitoring and Power Fault Registers
Parameter Power Monitor Pointer Line Power Monitor Output Description/ Range 0 to 5 points to Q1 to Q6, respectively 0 to 7.8 W for Q1, Q2, Q5, Q6 0 to 0.9 W for Q3, Q4 0 to 7.8 W 0 to 0.9 W 0 to 7.8 W Resolution n/a 30.4 mW 3.62 mW Register Bits PWRMP[2:0] PWROM[7:0] Location* Direct Register 76 Direct Register 77
Power Alarm Threshold, Q1 & Q2 Power Alarm Threshold, Q3 & Q4 Power Alarm Threshold, Q5 & Q6 Thermal LPF Pole, Q1 & Q2 Thermal LPF Pole, Q3 & Q4 Thermal LPF Pole, Q5 & Q6 Power Alarm Interrupt Pending
30.4 mW 3.62 mW 30.4 mW
PPT12[7:0] PPT34[7:0] PPT56[7:0] NQ12[7:0] NQ34[7:0] NQ56[7:0]
Indirect Register 32 Indirect Register 33 Indirect Register 34 Indirect Register 37 Indirect Register 38 Indirect Register 39 Direct Register 19
see equation above see equation above see equation above Bits 2 to 7 correspond to Q1 to Q6, respectively Bits 2 to 7 correspond to Q1 to Q6, respectively 0 = manual mode 1 = enter open state upon power alarm n/a
QnAP[n+1], where n = 1 to 6 QnAE[n+1], where n = 1 to 6 AOPN
Power Alarm Interrupt Enable
n/a
Direct Register 22
Power Alarm Automatic/Manual Detect
n/a
Direct Register 67
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. An "indirect" register is one that is accessed using the indirect access registers (direct registers 28 through 31).
Preliminary Rev. 0.96
21
Si3230
LCS LVS Input Signal Processor ISP_OUT Digital LPF + Debounce Filter - NCLR LFS LCVE HYSTEN Loop Closure Threshold LCDI LCIE LCR LCIP
Interrupt Logic
LCRT LCRTL
Figure 9. Loop Closure Detection
2.1.6. Loop Closure Detection 2.1.8. Voltage-Based Loop Closure Detection
A loop closure event signals that the terminal equipment Optional voltage-based loop closure detection mode is has gone off-hook during on-hook transmission or on- enabled by setting LCVE = 1 (direct Register 108, hook active states. The ProSLIC performs loop closure bit 2). In this mode, the loop voltage is compared to the detection digitally using its on-chip monitor A/D loop closure threshold register (LCRT), which converter. The functional blocks required to implement represents a minimum voltage threshold instead of a loop closure detection are shown in Figure 9. The maximum current threshold. If hysteresis is also primary input to the system is the Loop Current Sense enabled, LCRT represents the upper voltage boundary, value provided in the LCS register (direct Register 79). and LCRTL represents the lower voltage boundary for The LCS value is processed in the Input Signal hysteresis. Although voltage-based loop closure Processor when the ProSLIC is in the on-hook detection is an option, the default current-based loop transmission or on-hook active linefeed state, as closure detection is recommended. indicated by the Linefeed Shadow register, LFS[2:0] Table 23. Register Set for Loop (direct Register 64). The data then feeds into a Closure Detection programmable digital low-pass filter, which removes unwanted ac signal components before threshold Parameter Register Location detection. Loop Closure LCIP Direct Reg. 19 The output of the low-pass filter is compared to a Interrupt Pending programmable threshold, LCRT (indirect register 28). LCIE Direct Reg. 22 The threshold comparator output feeds a programmable Loop Closure Interrupt Enable debouncing filter. The output of the debouncing filter remains in its present state unless the input remains in Loop Closure Threshold LCRT[5:0] Indirect Reg. 28 LCRTL[5:0] Indirect Reg. 43 the opposite state for the entire period of time Loop Closure programmed by the loop closure debounce interval, Threshold--Lower LCDI (direct Register 69). If the debounce interval has Loop Closure Filter NCLR[12:0] Indirect Reg. 35 been satisfied, the LCR bit will be set to indicate that a Coefficient valid loop closure has occurred. A loop closure interrupt Loop Closure Detect LCR Direct Reg. 68 is generated if enabled by the LCIE bit (direct Status (monitor only) Register 22). Table 23 lists the registers that must be Loop Closure Detect LCDI[6:0] Direct Reg. 69 written or monitored to correctly detect a loop closure Debounce Interval condition. Hysteresis Enable HYSTEN Direct Reg. 108 2.1.7. Loop Closure Threshold Hysteresis Voltage-Based Loop LCVE Direct Reg. 108 Programmable hysteresis to the loop closure threshold Closure can be enabled by setting HYSTEN = 1 (direct Register 108, bit 0). The hysteresis is defined by LCRT (indirect Register 28) and LCRTL (indirect Register 43), which set the upper and lower bounds, respectively.
22
Preliminary Rev. 0.96
Si3230
2.1.9. Linefeed Calibration An internal calibration algorithm corrects for internal and external component errors. The calibration is initiated by setting the CAL bit in direct Register 96. Upon completion of the calibration cycle, this bit is automatically reset. It is recommended that a calibration be executed following system power-up. Upon release of the chip reset, the Si3230 will be in the open state. After powering up the dc-dc converter and allowing it to settle for time (tsettle) the calibration can be initiated. Additional calibrations may be performed, but only one calibration should be necessary as long as the system remains powered up. During calibration, VBAT, VTIP, and VRING voltages are controlled by the calibration engine to provide the correct external voltage conditions for the algorithm. Calibration should be performed in the on-hook state. RING or TIP must not be connected to ground during the calibration. Consider this when selecting the appropriate input voltage and power rating for the VDC power supply. For this solution, a PNP power BJT (Q7) switches the current flow through low ESR inductor L1. The Si3230 uses the DCDRV and DCFF pins to switch Q7 on and off. DCDRV controls Q7 through NPN BJT Q8. DCFF is ac coupled to Q7 through capacitor C10 to assist R16 in turning off Q7. Therefore, DCFF must have opposite polarity to DCDRV, and the Si3230 (not Si3230M) must be used. 2.2.3. MOSFET/Transformer Circuit Option Using Si3230M The MOSFET/transformer circuit option, as defined in Figure 5, offers higher power efficiencies across a larger input voltage range. Depending on the transformers primary inductor value and the switching frequency, the input voltage (VDC) can range from 3.3 V to 35 V. Therefore, it is possible to power the entire ProSLIC solution from a single 3.3 V or 5 V power supply. By nature of a dc-dc converter's operation, peak and average input currents can become large with small input voltages. Consider this when selecting the appropriate input voltage and power rating for the VDC power supply (number of REN supported). For this solution, an n-channel power MOSFET (M1) switches the current flow through a power transformer T1. T1 is specified in Application Note 45 (AN45), and includes several taps on the primary side to facilitate a wide range of input voltages. The Si3230M version of the Si3230 must be used for the application circuit depicted in Figure 5 because the DCFF pin is used to drive M1 directly and therefore must be the same polarity as DCDRV. DCDRV is not used in this circuit option; connecting DCFF and DCDRV together is not recommended. 2.2.4. DC-DC Converter Architecture The control logic for a pulse width modulated (PWM) dcdc converter is incorporated in the Si3230. Output pins, DCDRV and DCFF, are used to switch a bipolar transistor or MOSFET. The polarity of DCFF is opposite to that of DCDRV. The dc-dc converter circuit is powered on when the DCOF bit in the Power Down Register (direct Register 14, bit 4) is cleared to 0. The switching regulator circuit within the Si3230 is a high performance, pulse-width modulation controller. The control pins are driven by the PWM controller logic in the Si3230. The regulated output voltage (VBAT) is sensed by the SVBAT pin and is used to detect whether the output voltage is above or below an internal reference for the desired battery voltage. The dc monitor pins SDCH and SDCL monitor input current and
2.2. Battery Voltage Generation and Switching
The Si3230 integrates a dc-dc converter controller that dynamically regulates a single output voltage. This eliminates the need to supply large external battery voltages. Instead, it converts a single positive input voltage into the real-time battery voltage needed for any given state according to programmed linefeed parameters. 2.2.1. DC-DC Converter General Description The dc-dc converter dynamically generates the large negative voltages required to operate the linefeed interface. The Si3230 acts as the controller for a buckboost dc-dc converter that converts a positive dc voltage into the desired negative battery voltage. In addition to eliminating external power supplies, this allows the Si3230 to dynamically control the battery voltage to the minimum required for any given mode of operation. Extensive design guidance can be obtained from Application Note 45 (AN45) and from an interactive dcdc converter design spreadsheet. Both of these documents are available on the Silicon Laboratories website (www.silabs.com). 2.2.2. BJT/Inductor Circuit Using Si3230 The BJT/Inductor circuit, as defined in Figure 4, offers a flexible, low-cost solution. Depending on selected L1 inductance value and the switching frequency, the input voltage (VDC) can range from 5 V to 30 V. By nature of a dc-dc converter's operation, peak and average input currents can become large with small input voltages.
Preliminary Rev. 0.96
23
Si3230
voltage to the dc-dc converter external circuitry. If an overload condition is detected, the PWM controller will turn off the switching transistor for the remainder of a PWM period to prevent damage to external components. It is important that the proper value of R18 be selected to ensure safe operation. Guidance is given in Application Note 45 (AN45). The PWM controller operates at a frequency set by the dc-dc Converter PWM register (direct Register 92). During a PWM period the outputs of the control pins DCDRV and DCFF are asserted for a time given by the read-only PWM Pulse Width register (direct Register 94). The dc-dc converter must be off for some time in each cycle to allow the inductor or transformer to transfer its stored energy to the output capacitor, C9. This minimum off time can be set through the dc-dc Converter Switching Delay register, (direct Register 93). The number of 16.384 MHz clock cycles that the controller is off is equal to DCTOF (bits 0 through 4) plus 4. If the dc Monitor pins detect an overload condition, the dc-dc converter interrupts its conversion cycles regardless of the register settings to prevent component damage. These inputs should be calibrated by writing the DCCAL bit (bit 7) of the dc-dc Converter Switching Delay register, direct Register 93, after the dc-dc converter has been turned on. Because the Si3230 dynamically regulates its own battery supply voltage using the dc-dc converter controller, the battery voltage (VBAT) is offset from the negative-most terminal by a programmable voltage (VOV) to allow voltage headroom for carrying audio signals. As mentioned previously, the Si3230 dynamically adjusts VBAT to suit the particular circuit requirement. To illustrate this, the behavior of VBAT in the active state is shown in Figure 10. In the active state, the TIP-to-RING open circuit voltage is kept at VOC in the constant voltage region while the regulator output voltage, VBAT = VCM + VOC + VOV. When the loop current attempts to exceed ILIM, the dc line driver circuit enters constant current mode allowing the TIP to RING voltage to track RLOOP. As the TIP terminal is kept at a constant voltage, it is the RING terminal voltage that tracks RLOOP and, as a result, the |VBAT| voltage will also track RLOOP. In this state, |VBAT| = ILIM x RLOOP + VCM +VOV. As RLOOP decreases below the VOC/ILIM mark, the regulator output voltage can continue to track RLOOP (TRACK = 1), or the RLOOP tracking mechanism is stopped when |VBAT| = |VBATL| (TRACK = 0). The former case is the more common application and provides the maximum power dissipation savings. In principle, the regulator output voltage can go as low as |VBAT| = VCM+ VOV, offering significant power savings. When TRACK = 0, |VBAT| will not decrease below VBATL. The RING terminal voltage, however, continues to decrease with decreasing RLOOP. The power dissipation on the NPN bipolar transistor driving the RING terminal can become large and may require a higher power rating device. The non-tracking mode of operation is required by specific terminal equipment which, in order to initiate certain data transmission modes, goes briefly on-hook to measure the line voltage to determine whether there is any other off-hook terminal equipment on the same line. TRACK = 0 mode is desired since the regulator output voltage has long settling time constants (on the order of tens of milliseconds) and cannot change rapidly for TRACK = 1 mode. Therefore, the brief on-hook voltage measurement would yield approximately the same voltage as the off-hook line voltage and would cause the terminal equipment to incorrectly sense another offhook terminal.
24
Preliminary Rev. 0.96
Si3230
VOC
Constant I Region
ILIM VCM
Constant V Region
RLOOP VTIP
TR AC
VBATL
K= 1
|VTIP - VRING|
VOV
VOC
TRACK=0
VOV
VRING VBAT
V
Figure 10. VTIP, VRING, and VBAT in the Forward Active State Table 24. Associated Relevant DC-DC Converter Registers
Parameter DC-DC Converter Power-off Control DC-DC Converter Calibration Enable/Status DC-DC Converter PWM Period DC-DC Converter Min. Off Time High Battery Voltage--VBATH Low Battery Voltage--VBATL VOV Range n/a n/a 0 to 15.564 us (0 to 1.892 us) + 4 ns 0 to -94.5 V 0 to -94.5 V 0 to -9 V or 0 to -13.5 V Resolution n/a n/a 61.035 ns 61.035 ns 1.5 V 1.5 V 1.5 V Register Bit DCOF DCCAL DCN[7:0] DCTOF[4:0] VBATH[5:0] VBATL[5:0] VMIND[3:0] VOV Location Direct Register 14 Direct Register 93 Direct Register 92 Direct Register 93 Direct Register 74 Direct Register 75 Indirect Register 41 Direct Register 66
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. An "indirect" register is one that is accessed using the indirect access registers (direct registers 28 through 31).
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2.2.5. DC-DC Converter Enhancements There are two enhancements to the dc-dc converter. The first is a multi-threshold error control algorithm that enables the dc-dc converter to adjust more quickly to voltage changes. This option is enabled by setting DCSU = 1 (direct Register 108, bit 5). The second enhancement is an audio band filter that removes audio band noise from the dc-dc converter control loop. This option is enabled by setting DCFIL = 1 (direct Register 108, bit 1). 2.2.6. DC-DC Converter During Ringing When the ProSLIC enters the ringing state, it requires voltages well above those used in the active mode. The voltage to be generated and regulated by the dc-dc converter during a ringing burst is set using the VBATH register (direct Register 74). VBATH can be set between 0 and -94.5 V in 1.5 V steps. To avoid clipping the ringing signal, VBATH must be set larger than the ringing amplitude. At the end of each ringing burst the dc-dc converter adjusts back to active state regulation as described above.
8 kHz Clock OnE OZn Zero Cross Zero Cross Logic OSSn
Enable
2.3. Tone Generation
Two digital tone generators are provided in the ProSLIC. They allow the generation of a wide variety of single or dual tone frequency and amplitude combinations and spare the user the effort of generating the required POTS signaling tones on the PCM highway. DTMF, FSK (caller ID), call progress, and other tones can all be generated on-chip. 2.3.1. Tone Generator Architecture A simplified diagram of the tone generator architecture is shown in Figure 11. The oscillator, active/inactive timers, interrupt block, and signal routing block are connected to give the user flexibility in creating audio signals. Control and status register bits are placed in the figure to indicate their association with the tone generator architecture. These registers are described in more detail in Table 25.
8 kHz Clock
16-Bit Modulo Counter
OAT Expire OIT Expire
Load Logic
Two-Pole Resonance Register Oscillator
Load
to TX Path
Signal Routing
to RX Path
OATn OATnE OITn OITnE INT Logic INT Logic
OSCn OnIP REL* OnSO OnIE OnAP OSCnY OSCnX
OnAE *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively
Figure 11. Simplified Tone Generator Diagram
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2.3.2. Oscillator Frequency and Amplitude Each of the two tone generators contains a two-pole resonate oscillator circuit with a programmable frequency and amplitude, which are programmed via indirect registers OSC1, OSC1X, OSC1Y, OSC2, OSC2X, and OSC2Y. The sample rate for the two oscillators is 8000 Hz. The equations are as follows: coeffn = cos(2 fn/8000 Hz), where fn is the frequency to be generated; OSCn = coeffn x (215);
Desired V rms 1 15 1 - coeff OSCnX = -- x ----------------------- x ( 2 - 1 ) x -----------------------------------4 1.11 V rms 1 + coeff
where desired Vrms is the amplitude to be generated; OSCnY = 0, n = 1 or 2 for oscillator 1 or oscillator 2, respectively. For example, in order to generate a DTMF digit of 8, the two required tones are 852 Hz and 1336 Hz. Assuming the generation of half-scale values (ignoring twist) is desired, the following values are calculated:
2852 coeff 1 = cos ---------------- = 0.78434 8000 OSC1 = 0.78434 ( 2 ) = 25701 = 6465h 1 15 OSC1X = -- x 0.21556 x ( 2 - 1 ) x 0.5 = 1424 = 590h -------------------4 1.78434
15
To enable automatic cadence for tone generator 1, define the OAT1 and OIT1 registers and then set the O1TAE bit (direct Register 32, bit 4) and O1TIE bit (direct Register 32, bit 3). This enables each of the timers to control the state of the Oscillator Enable bit, O1E (direct Register 32, bit 2). The 16-bit counter will begin counting until the active timer expires, at which time the 16-bit counter will reset to zero and begin counting until the inactive timer expires. The cadence continues until the user clears the O1TAE and O1TIE control bits. The zero crossing detect feature can be implemented by setting the OZ1 bit (direct Register 32, bit 5). This ensures that each oscillator pulse ends without a dc component. The timing diagram in Figure 12 is an example of an output cadence using the zero crossing feature. One-shot oscillation can be achieved by enabling O1E and O1TAE. Direct control over the cadence can be achieved by controlling the O1E bit (direct Register 32, bit 2) directly if O1TAE and O1TIE are disabled. The operation of tone generator 2 is identical to that of tone generator 1 using its respective control registers.
Note: Tone Generator 2 should not be enabled simultaneously with the ringing oscillator due to resource sharing within the hardware.
OSC1Y = 0
21336 coeff2 = cos ------------------- = 0.49819 8000
Continuous phase frequency-shift keying (FSK) waveforms may be created using tone generator 1 (not available on tone generator 2) by setting the REL bit (direct Register 32, bit 6), which enables reloading of the OSC1, OSC1X, and OSC1Y registers at the expiration of the active timer (OAT1).
OSC2 = 0.49819 (215) = 16324 = 3FC4h
15 1 OSC2X = -- x 0.50181 x ( 2 - 1 ) x 0.5 = 2370 = 942h -------------------4 1.49819
OSC2Y = 0 The computed values above would be written to the corresponding registers to initialize the oscillators. Once the oscillators are initialized, the oscillator control registers can be accessed to enable the oscillators and direct their outputs. 2.3.3. Tone Generator Cadence Programming Each of the two tone generators contains two timers, one for setting the active period and one for setting the inactive period. The oscillator signal is generated during the active period and suspended during the inactive period. Both the active and inactive periods can be programmed from 0 to 8 seconds in 125 s steps. The active period time interval is set using OAT1 (direct registers 36 and 37) for tone generator 1 and OAT2 (direct registers 40 and 41) for tone generator 2.
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Table 25. Associated Tone Generator Registers
Tone Generator 1 Parameter Oscillator 1 Frequency Coefficient Oscillator 1 Amplitude Coefficient Oscillator 1 initial phase coefficient Oscillator 1 Active Timer Oscillator 1 Inactive Timer Oscillator 1 Control Description / Range Sets oscillator frequency Sets oscillator amplitude Sets initial phase 0 to 8 seconds 0 to 8 seconds Status and control registers Tone Generator 2 Parameter Oscillator 2 Frequency Coefficient Oscillator 2 Amplitude Coefficient Oscillator 2 initial phase coefficient Oscillator 2 Active Timer Oscillator 2 Inactive Timer Oscillator 2 Control Description/Range Sets oscillator frequency Sets oscillator amplitude Sets initial phase 0 to 8 seconds 0 to 8 seconds Status and control registers Register OSC2[15:0] OSC2X[15:0] OSC2Y[15:0] OAT2[15:0] OIT2[15:0] OSS2, OZ2, O2TAE, O2TIE, O2E, O2SO[1:0] Location Indirect Register 16 Indirect Register 17 Indirect Register 18 Direct Registers 40 & 41 Direct Register 42 & 43 Direct Register 33 Register Bits OSC1[15:0] OSC1X[15:0] OSC1Y[15:0] OAT1[15:0] OIT1[15:0] OSS1, REL, OZ1, O1TAE, O1TIE, O1E, O1SO[1:0] Location Indirect Register 13 Indirect Register 14 Indirect Register 15 Direct Registers 36 & 37 Direct Register 38 & 39 Direct Register 32
O1E
0,1
...
..., OAT1 0,1 ...
..., O IT1 0,1 ...
..., OAT1 0,1 ...
... ...
OSS1
Tone G en. 1 Signal O utput
Figure 12. Tone Generator Timing Diagram
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2.3.4. Enhanced FSK Waveform Generation Silicon revisions C and higher support enhanced FSK generation capabilities, which can be enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REN = 1 (direct Register 32, bit 6). In this mode, the user can define mark (1) and space (0) attributes once during initialization by defining indirect registers 99-104. The user need only indicate 0-to-1 and 1-to-0 transitions in the information stream. By writing to FSKDAT (direct Register 52), this mode applies a 24 kHz sample rate to tone generator 1 to give additional resolution to timers and frequency generation. Application Note 32 gives detailed instructions on how to implement FSK in this mode. Additionally, sample source code is available from Silicon Laboratories upon request. 2.3.5. Tone Generator Interrupts Both the active and inactive timers can generate their own interrupt to signal "on/off" transitions to the software. The timer interrupts for tone generator 1 can be individually enabled by setting the O1AE and O1IE bits (direct Register 21, bits 0 and 1, respectively). Timer interrupts for tone generator two are O2AE and O2IE (direct Register 21, bits 2 and 3, respectively). A pending interrupt for each of the timers is determined by reading the O1AP, O1IP, O2AP, and O2IP bits in the Interrupt Status 1 register (direct Register 18, bits 0 through 3, respectively).
2.4. Ringing Generation
The ProSLIC provides fully programmable internal balanced ringing with or without a dc offset to ring a wide variety of terminal devices. All parameters associated with ringing are software programmable: ringing frequency, waveform, amplitude, dc offset, and ringing cadence. Both sinusoidal and trapezoidal ringing waveforms are supported, and the trapezoidal crest factor is programmable. Ringing signals of up to 88 V peak or more can be generated, enabling the ProSLIC to drive a 5 REN (1380 + 40 F) ringer load across loop lengths of 2000 feet (160 ) or more. 2.4.1. Ringing Architecture The ringing generator architecture is nearly identical to that of the tone generator. The sinusoid ringing waveform is generated using an internal two-pole resonance oscillator circuit with programmable frequency and amplitude. However, since ringing frequencies are very low compared to the audio band signaling frequencies, the ringing waveform is generated at a 1 kHz rate instead of 8 kHz. The ringing generator has two timers that function the same as for the tone generator timers. They allow on/off cadence settings up to 8 seconds on/ 8 seconds off. In addition to controlling ringing cadence, these timers control the transition into and out of the ringing state. Table 26 summarizes the list of registers used for ringing generation.
Note: Tone generator 2 should not be enabled concurrently with the ringing generator due to resource sharing within the hardware.
Table 26. Registers for Ringing Generation
Parameter Ringing Waveform Ringing Voltage Offset Enable Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control (Initiates Ringing State) High Battery Voltage Ringing dc voltage offset Range/ Description Sine/Trapezoid Enabled/ Disabled Enabled/ Disabled Enabled/ Disabled Enabled/ Disabled 0 to 8 seconds 0 to 8 seconds Ringing State = 100b 0 to -94.5 V 0 to 94.5 V Register Bits TSWS RVO RTAE RTIE ROE RAT[15:0] RIT[15:0] LF[2:0] VBATH[5:0] ROFF[15:0] Location Direct Register 34 Direct Register 34 Direct Register 34 Direct Register 34 Direct Register 34 Direct Registers 48 and 49 Direct Registers 50 and 51 Direct Register 64 Direct Register 74 Indirect Register 19
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Table 26. Registers for Ringing Generation (Continued)
Ringing frequency Ringing amplitude Ringing initial phase 15 to 100 Hz 0 to 94.5 V Sets initial phase for sinewave and period for trapezoid 0 to 22.5 V RCO[15:0] RNGX[15:0] RNGY[15:0] Indirect Register 20 Indirect Register 21 Indirect Register 22
Common Mode Bias Adjust During Ringing
VCMR[3:0]
Indirect Register 40
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. An "indirect" register is one that is accessed using the indirect access registers (direct registers 28 through 31).
When the ringing state is invoked by writing LF[2:0] = 100 (direct Register 64), the ProSLIC will go into the ringing state and start the first ring. At the expiration of RAT, the ProSLIC will turn off the ringing waveform and will go to the on-hook transmission state. At the expiration of RIT, ringing will again be initiated. This process will continue as long as the two timers are enabled and the Linefeed Control register is set to the ringing state. 2.4.2. Sinusoidal Ringing To configure the ProSLIC for sinusoidal ringing, the frequency and amplitude are initialized by writing to the following indirect registers: RCO, RNGX, and RNGY. The equations for RCO, RNGX, RNGY are as follows:
RCO = coeff x ( 2 )
15
In addition, the user must select the sinusoidal ringing waveform by writing TSWS = 0 (direct Register 34, bit 0). 2.4.3. Trapezoidal Ringing In addition to the sinusoidal ringing waveform, the ProSLIC supports trapezoidal ringing. Figure 13 illustrates a trapezoidal ringing waveform with offset VROFF.
VTIP-RING
VROFF T=1/freq
tRISE
where
2f coeff = cos ---------------------- 1000 Hz
time
and f = desired ringing frequency in hertz.
1 15 Desired V PK ( 0 to 94.5 V ) 1 - coeff RNGX = -- x ----------------------- x 2 x ----------------------------------------------------------------------4 96 V 1 + coeff RNGY = 0
Figure 13. Trapezoidal Ringing Waveform
To configure the ProSLIC for trapezoidal ringing, the user should follow the same basic procedure as in the Sinusoidal Ringing section, but using the following equations:
1 RNGY = -- x Period x 8000 2 Desired V PK 15 RNGX = ----------------------------------- x ( 2 ) 96 V 2 x RNGX RCO = -------------------------------t RISE x 8000
In selecting a ringing amplitude, the peak TIP-to-RING ringing voltage must be greater than the selected onhook line voltage setting (VOC, direct Register 72). For example, to generate a 70 VPK 20 Hz ringing signal, the equations are as follows:
2 x 20coeff = cos ---------------------- = 0.99211 1000 Hz RCO = 0.99211 x ( 2 ) = 32509 = 7EFDh 1 15 70 RNGX = -- x 0.00789 x 2 x ----- = 376 = 0177h -------------------4 96 1.99211 RNGY = 0
15
RCO is a value which is added or subtracted from the waveform to ramp the signal up or down in a linear fashion. This value is a function of rise time, period, and
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amplitude, where rise time and period are related through the following equation for the crest factor of a trapezoidal waveform.
3 1t RISE = -- T 1 - ---------- 2 4 CF
equations below.
V AC,PK N REN I LOAD,PK = ------------------ + I OS = V AC,PK x ----------------- + I OS R LOAD 6.9 k
where: NREN is the ringing REN load (max value = 5), IOS is the offset current flowing in the line driver circuit (max value = 2 mA), and VAC,PK = amplitude of the ac ringing waveform. It is good practice to provide a buffer of a few more milliamperes for ILOAD,PK to account for possible line leakages, etc. The total ILOAD,PK current should be smaller than 80 mA.
+1 V OVR = I LOAD,PK x ------------ x ( 80.6 + 1 V )
where T = ringing period, and CF = desired crest factor. For example, to generate a 71 VPK, 20 Hz ringing signal, the equations are as follows:
1 1RNGY ( 20 Hz ) = -- x --------------- x 8000 = 200 = C8h 2 20 Hz 71 15 RNGX ( 71 V PK ) = ----- x 2 = 24235 = 5EABh 96
For a crest factor of 1.3 and a period of 0.05 seconds (20 Hz), the rise time requirement is 0.0153 seconds.
RCO ( 20 Hz, 1.3 crest factor ) 2 x 24235 = ------------------------------------- = 396 = 018Ch 0.0153 x 8000
where is the minimum expected current gain of transistors Q5 and Q6. The minimum value for VBATH is therefore given by the following:
VBATH = V AC,PK + V ROFF + V OVR
In addition, the user must select the trapezoidal ringing waveform by writing TSWS = 1 in direct Register 34. 2.4.4. Ringing DC voltage Offset A dc offset can be added to the ac ringing waveform by defining the offset voltage in ROFF (indirect Register 19). The offset, VROFF, is added to the ringing signal when RVO is set to 1 (direct Register 34, bit 1). The value of ROFF is calculated as follows:
V ROFF 15 ROFF = ----------------- x 2 96
The ProSLIC is designed to create a fully balanced ringing waveform, meaning that the TIP and RING common mode voltage, (VTIP + VRING)/2, is fixed. This voltage is referred to as VCM_RING and is automatically set to the following:
VBATH - VCMR VCM_RING = --------------------------------------------2
2.4.5. Linefeed Considerations During Ringing Care must be taken to keep the generated ringing signal within the ringing voltage rails (GNDA and VBAT) to maintains proper biasing of the external bipolar transistors. If the ringing signal nears the rails, a distorted ringing signal and excessive power dissipation in the external transistors will result. To prevent this invalid operation, set the VBATH value (direct Register 74) to a value higher than the maximum peak ringing voltage. The discussion below outlines the considerations and equations that govern the selection of the VBATH setting for a particular desired peak ringing voltage. First, the required amount of ringing overhead voltage, VOVR, is calculated based on the maximum value of current through the load, ILOAD,PK, the minimum current gain of Q5 and Q6, and a reasonable voltage required to keep Q5 and Q6 out of saturation. For ringing signals up to VPK = 87 V, VOVR = 7.5 V is a safe value. However, to determine VOVR for a specific case, use the
VCMR is an indirect register which provides the headroom by the ringing waveform with respect to the VBATH rail. The value is set as a 4-bit setting in indirect Register 40 with an LSB voltage of 1.5 V/LSB. Register 40 should be set with the calculated VOVR to provide voltage headroom during ringing. Silicon revisions C and higher support the option to briefly increase the maximum differential current limit between the voltage transition of TIP and RING from ringing to a dc linefeed state. This mode is enabled by setting ILIMEN = 1 (direct Register 108, bit 7). 2.4.6. Ring Trip Detection A ring trip event signals that the terminal equipment has gone off-hook during the ringing state. The ProSLIC performs ring trip detection digitally using its on-chip monitor A/D converter. The functional blocks required to implement ring trip detection is shown in Figure 14. The primary input to the system is the Loop Current Sense value provided by the current monitoring circuitry and reported in direct Register 79. LCS data is processed by the input signal processor when the ProSLIC is in the
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ringing state as indicated by the Linefeed Shadow register (direct Register 64). The data then feeds into a programmable digital low pass filter, which removes unwanted ac signal components before threshold detection. The output of the low pass filter is compared to a programmable threshold, RPTP (indirect Register 29). The threshold comparator output feeds a programmable debouncing filter. The output of the debouncing filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the ring trip debounce interval,
Input Signal Processor
RTDI[6:0] (direct Register 70). If the debounce interval has been satisfied, the RTP bit of direct Register 68 will be set to indicate that a valid ring trip has occurred. A ring trip interrupt is generated if enabled by the RTIE bit (direct Register 22). Table 27 lists the registers that must be written or monitored to correctly detect a ring trip condition. The recommended values for RPTP, NRTP, and RTDI vary according to the programmed ringing frequency. Register values for various ringing frequencies are given in Table 28.
LCS
ISP_OUT
Digital LPF
+
DBIRAW
Debounce Filter
RTP
Interrupt Logic
RTIP
- NRTP LFS Ring Trip Threshold RTDI RTIE
RPTP
Figure 14. Ring Trip Detector
Table 27. Associated Registers for Ring Trip Detection
Parameter Ring Trip Interrupt Pending Ring Trip Interrupt Enable Ring Trip Detect Debounce Interval Ring Trip Threshold Ring Trip Filter Coefficient Ring Trip Detect Status (monitor only) Register RTIP RTIE RTDI[6:0] RPTP[5:0] NRTP[12:0] RTP Location Direct Register 19 Direct Register 22 Direct Register 70 Indirect Register 29 Indirect Register 36 Direct Register 68
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. An "indirect" register is one that is accessed using the indirect access registers (direct registers 28 through 31).
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Table 28. Recommended Ring Trip Values for Ringing
Ringing Frequency Hz 16.667 20 30 40 50 60 decimal 64 100 112 128 213 256 NRTP hex 0200 0320 0380 0400 06A8 0800 decimal 34 mA 34 mA 34 mA 34 mA 34 mA 34 mA RPTP hex 3600 3600 3600 3600 3600 3600 decimal 15.4 ms 12.3 ms 8.96 ms 7.5 ms 5 ms 4.8 ms RTDI hex 0F 0B 09 07 05 05
2.5. Pulse Metering Generation
There is an additional tone generator suitable for generating tones above the audio frequency. This oscillator is provided for the generation of billing tones which are typically 12 kHz or 16 kHz. The generator follows the same algorithm as described in "2.3. Tone Generation" on page 26 with the exception that the sample rate for computation is 64 kHz instead of 8 kHz. The equations are as follows:
2f coeff = cos ------------------------- 64000 Hz PLSCO = coeff x ( 2
15
Desired V rms 1 1 - coeff 15 PLSX = -- ----------------------- x ( 2 - 1 ) x ------------------------------------------4 1 + coeff Full Scale V rms
where full scale Vrms = 0.85 Vrms for a matched load. The initial phase of the pulse metering signal is set to 0 internally so there is no register to serve this purpose. The pulse metering generator timers and associated pulse metering timer registers are similar to that of the tone generators. These timers count 8 kHz sample periods like the other tones even though the sinusoid is generated at 64 kHz.
- 1)
Table 29. Associated Pulse Metering Generator Registers
Parameter Pulse Metering Frequency Coefficient Pulse Metering Amplitude Coefficient Pulse Metering Attack/Decay Ramp Rate Pulse Metering Active Timer Pulse Metering Inactive Timer Pulse Metering Control Description / Range Sets oscillator frequency Sets oscillator amplitude 0 to PLSX (full amplitude) 0 to 8 seconds 0 to 8 seconds Status and control registers Register Bits PLSCO[15:0] PLSX[15:0] PLSD[15:0] PAT[15:0] PIT[15:0] PSTAT, PMAE, PMIE, PMOE Location Indirect Register 25 Indirect Register 24 Indirect Register 23 Direct Registers 44 & 45 Direct Register 46 & 47 Direct Register 35
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. An "indirect" register is one that is accessed using the indirect access registers (direct registers 28 through 31).
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The pulse metering oscillator has a volume envelope (linear ramp) on the on/off transitions of the oscillator. The volume value is incremented by the value in the PLSD register (indirect Register 23) at an 8 kHz rate. The sinusoidal generator output is multiplied by this volume before being sent to the DAC. The volume will ramp from 0 to 7FFF in increments of PLSD so the value of PLSD will set the slope of the ramp. When the pulse metering signal is turned off, the volume will ramp to 0 by decrementing according to the value of PLSD.
Pulse Metering Oscillator
2.6. DTMF Detection
The dual-tone multi-frequency (DTMF) tone signaling standard is also known as touch tone. It is an in-band signaling system used to replace the pulse-dial signaling standard. In DTMF, two tones are used to generate a DTMF digit. One tone is chosen from four possible row tones, and one tone is chosen from four possible column tones. The sum of these tones constitutes one of 16 possible DTMF digits. 2.6.1. DTMF Detection Architecture DTMF detection is performed using a modified Goertzel algorithm to compute the dual frequency tone (DFT) for each of the eight DTMF frequencies as well as their second harmonics. At the end of the DFT computation, the squared magnitudes of the DFT results for the eight DTMF fundamental tones are computed. The row results are sorted to determine the strongest row frequency; the column frequencies are sorted as well. At the completion of this process, a number of checks are made to determine whether the strongest row and column tones constitute a DTMF digit. The detection process is performed twice within the 45 ms minimum tone time. A digit must be detected on two consecutive tests following a pause to be recognized as a new digit. If all tests pass, an interrupt is generated, and the DTMF digit value is loaded into the DTMF register. If tones are occurring at the maximum rate of 100 ms per digit, the interrupt must be serviced within 85 ms so that the current digit is not overwritten by a new one. There is no buffering of the digit information.
X
Volum e 8 Khz
To DAC
+/-
PLSD
Clip to 7FFF or 0
Figure 15. Pulse Metering Volume Envelope
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Transmit Path HYBP From Billing Tone DAC H
Off Chip
On Chip
ATX
+-
A/D
Decimation Filter
THPF
ADCG
DTMF Decoder
H
HYBA
TIP RING
XAC D/A RAC From Billing Tone DAC
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-
ARX
+
Interpolation Filter
RHPF
DACG
Dual Tone Generator
Ibuf
Gm
Figure 16. AC Signal Path Block Diagram
Si3230
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2.7. Two-Wire Impedance Matching
The ProSLIC provides on-chip programmable two-wire impedance settings to meet a wide variety of worldwide two-wire return loss requirements. The two-wire impedance is programmed by loading one of the eight available impedance values into the TISS[2:0] bits of the Two-Wire Impedance Synthesis Control register (direct Register 10). If direct Register 10 is not user-defined, the default setting of 600 will be loaded into the TISS register. Real and complex two-wire impedances are realized by internal feedback of a programmable amplifier (RAC) a switched capacitor network (XAC) and a transconductance amplifier (Gm). (See Figure 16.) RAC creates the real portion and XAC creates the imaginary portion of Gm's input. Gm then creates a current that models the desired impedance value to the subscriber loop. The differential ac current is fed to the subscriber loop via the ITIPP and IRINGP pins through an off-chip current buffer (IBUF), which is implemented using transistor Q1 and Q2 (see Figure on page 15). Gm is referenced to an off-chip resistor (R15). The ProSLIC also provides a means to compensate for degraded subscriber loop conditions involving excessive line capacitance (leakage). The CLC[1:0] bits of direct Register 10 increase the ac signal magnitude to compensate for the additional loss at the high end of the audio frequency range. The default setting of CLC[2:0] assumes no line capacitance. Silicon revisions C and higher support the option to remove the internal reference resistor used to synthesize ac impedances for 600 + 2.16 F and 900 + 2.16 F settings so that an external resistor reference may be used. This option is enabled by setting ZSEXT = 1 (direct Register 108, bit 4). The PLL clock synthesizer settles very quickly following power up. However, the settling time depends on the PCLK frequency and it can be approximately predicted by the following equation:
64 T SETTLE = ---------------F PCLK
2.9. Interrupt Logic
The ProSLIC is capable of generating interrupts for the following events: Loop current/ring ground detected Ring trip detected Power alarm DTMF digit detected (Si3230 and Si3211 only) Active timer 1 expired Inactive timer 1 expired Active timer 2 expired Inactive timer 2 expired Ringing active timer expired Ringing inactive timer expired Pulse metering active timer expired Pulse metering inactive timer expired Indirect register access complete The interface to the interrupt logic consists of six registers. Three interrupt status registers contain 1 bit for each of the above interrupt functions. These bits will be set when an interrupt is pending for the associated resource. Three interrupt enable registers also contain 1 bit for each interrupt function. In the case of the interrupt enable registers, the bits are active high. Refer to the appropriate functional description section for operational details of the interrupt functions. When a resource reaches an interrupt condition, it will signal an interrupt to the interrupt control block. The interrupt control block will then set the associated bit in the interrupt status register if the enable bit for that interrupt is set. The INT pin is a NOR of the bits of the interrupt status registers. Therefore, if a bit in the interrupt status registers is asserted, IRQ will assert low. Upon receiving the interrupt, the interrupt handler should read interrupt status registers to determine which resource is requesting service. To clear a pending interrupt, write the desired bit in the appropriate interrupt status register to 1. Writing a 0 has no effect. This provides a mechanism for clearing individual bits when multiple interrupts occur simultaneously. While the interrupt status registers are non-zero, the INT pin will remain asserted.
2.8. Clock Generation
The ProSLIC will generate the necessary internal clock frequencies from the PCLK input. PCLK must be synchronous to the 8 kHz FSYNC clock and run at one of the following rates: 256 kHz, 512 kHz, 768 kHz, 1.024 MHz, 1.536 MHz, 2.048 MHz, 4.096 MHz or 8.192 MHz. The ratio of the PCLK rate to the FSYNC rate is determined via a counter clocked by PCLK. The three-bit ratio information is automatically transferred into an internal register, PLL_MULT, following a reset of the ProSLIC. The PLL_MULT is used to control the internal PLL which multiplies PCLK as needed to generate 16.384 MHz rate needed to run the internal filters and other circuitry.
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Si3230
2.10. Serial Peripheral Interface
The control interface to the ProSLIC is a 4-wire interface modeled after commonly available micro-controller and serial peripheral devices. The interface consists of a clock (SCLK), chip select (CS), serial data input (SDI), and serial data output (SDO). Data is transferred a byte at a time with each register access consisting of a pair of byte transfers. Figures 17 and 18 illustrate read and write operation in the SPI bus. The first byte of the pair is the command/address byte. The MSB of this byte indicates register read when 1 and a register write when 0. The remaining seven bits of the command/address byte indicate the address of the register to be accessed. The second byte of the pair is the data byte. Because the falling edge of CS provides resynchronization of the SPI state machine in the event of a framing error, it is recommended (but not required) that CS be taken high between byte transfers as shown in Figures 17 and 18. During a read operation, the SDO becomes active and the 8-bit contents of the register are driven out MSB first. The SDO will be high impedence on either the falling edge of SCLK following the LSB, or the rising of CS as specified by the SPIM bit (direct Register 0, bit 6). SDI is a "don't care" during the data portion of read operations. During write operations, data is driven into the ProSLIC via the SDI pin MSB first. The SDO pin will remain high impedance during write operations. Data always transitions with the falling edge of the clock and is latched on the rising edge. The clock should return to a logic high when no transfer is in progress. Indirect registers are accessed through direct registers 29 through 30. Instructions on how to access them is described in "3. Control Registers" beginning on page 40. There are a number of variations of usage on this fourwire interface: Continuous clocking. During continuous clocking, the data transfers are controlled by the assertion of the CS pin. CS must assert before the falling edge of SCLK on which the first bit of data is expected during a read cycle, and must remain low for the duration of the 8-`bit transfer (command/address or data). SDI/SDO wired operation. Independent of the clocking options described, SDI and SDO can be treated as two separate lines or wired together if the master is capable of tristating its output during the data byte transfer of a read operation. Daisy chain mode. This mode allows communication with banks of up to eight ProSLIC devices using one chip select signal. When the SPIDC bit in the SPI Mode Select register is set, data transfer mode changes to a 3-byte operation: a chip select byte, an address/control byte, and a data byte. Using the circuit shown in Figure 19, a single device may select from the bank of devices by setting the appropriate chip select bit to 1. Each device uses the LSB of the chip select byte, shifts the data right by one bit, and passes the chip select byte using the SDITHRU pin to the next device in the chain. Address/control and data bytes are unaltered.
SCLK
Don't Care
CS
SDI
0
a6
a5
a4
a3
a2
a1
a0
d7
d6
d5
d4
d3
d2
d1
d0
SDO High Impedance
Figure 17. Serial Write 8-Bit Mode
Preliminary Rev. 0.96
37
Si3230
Don't Care
SCLK
CS
SDI
1
a6
a5
a4
a3
a2
a1
a0
Don't Care
SDO
High Impedance
d7
d6
d5
d4
d3
d2
d1
d0
Figure 18. Serial Read 8-Bit Mode
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Preliminary Rev. 0.96
Si3230
SDO CPU CS SDI
CS SDO
SDI
SDI0
SDITHRU
CS SDO
SDI
SDI1
SDITHRU
CS SDO
SDI
SDI2
SDITHRU
CS SDO
SDI
SDI3
SDITHRU
Chip Select Byte SCLK
Address Byte
Data Byte
SDI0
C7 C6 C5 C4 C3 C2 C1 C0
R/W
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
SDI1
- C7 C6 C5 C4 C3 C2 C1
R/W
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
SDI2
-
-
C7 C6 C5 C4 C3 C2
R/W
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
SDI3
-
-
-
C7 C6 C5 C4 C3
R/W
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
Note: During chip select byte, SDITHRU = SDI delayed by one SCLK. Each device daisy-chained looks at the LSB of the chip select byte for its chip select.
Figure 19. SPI Daisy Chain Mode
Preliminary Rev. 0.96
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Si3230
3. Control Registers
Note: Any register not listed here is reserved and must not be written.
Table 30. Direct Register Summary
Register Name 0 9 10 11 14 15 18 19 20 21 22 23 24 28 29 30 31 32 33 34 35 36 SPI Mode Select Audio Gain Control Two-Wire Impedance Synthesis Control Hybrid Control Power Down Control 1 Power Down Control 2 Interrupt Status 1 Interrupt Status 2 Interrupt Status 3 Interrupt Enable 1 Interrupt Enable 2 Interrupt Enable 3 Decode Status Indirect Data Access-- Low Byte Indirect Data Access-- High Byte Indirect Address Indirect Address Status Oscillators Oscillator 1 Control Oscillator 2 Control Ringing Oscillator Control Pulse Metering Oscillator Control Oscillator 1 Active Timer--Low Byte OSS1 OSS2 RSS PSTAT REL OZ1 OZ2 RDAC O1TAE O2TAE RTAE PMAE O1TIE O2TIE RTIE PMIE O1E O2E ROE PMOE O1SO[1:0] O2SO[1:0] RVO TSWS VAL Indirect Register Access IDA[7:0] IDA[15:8] IAA[7:0] IAS PMIE Q6AE PMAE Q5AE RGIE Q4AE RGAE Q3AE O2IE Q2AE PMIP Q6AP PMAP Q5AP Bit 7 SPIDC RXHP Bit 6 SPIM TXHP Bit 5 Setup PNI[1:0] Audio TXM RXM ATX[1:0] TISE ARX[1:0] TISS[2:0] HYBA[2:0] DCOF ADCON RGAP Q3AP MOF DACM O2IP Q2AP DACON O2AP Q1AP CMCP O2AE Q1AE CMCE BIASOF SLICOF GMM O1IP LCIP INDP O1IE LCIE INDE GMON O1AP RTIP DTMFP O1AE RTIE DTMFE CLC[1:0] HYBP[2:0] Powerdown PMON ADCM Interrupts RGIP Q4AP RNI[3:0] Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DIG[3:0]
OAT1[7:0]
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Preliminary Rev. 0.96
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Table 30. Direct Register Summary (Continued)
Register Name 37 38 39 40 41 42 43 44 Oscillator 1 Active Timer--High Byte Oscillator 1 Inactive Timer--Low Byte Oscillator 1 Inactive Timer--High Byte Oscillator 2 Active Timer--Low Byte Oscillator 2 Active Timer--High Byte Oscillator 2 Inactive Timer--Low Byte Oscillator 2 Inactive Timer--High Byte Pulse Metering Oscillator Active Timer-- Low Byte Pulse Metering Oscillator Active Timer-- High Byte Pulse Metering Oscillator Inactive Timer--Low Byte Pulse Metering Oscillator Inactive Timer--High Byte Ringing Oscillator Active Timer--Low Byte Ringing Oscillator Active Timer--High Byte Ringing Oscillator Inactive Timer--Low Byte Ringing Oscillator Inactive Timer--High Byte FSK Data SLIC 63 Loop Closure Debounce Interval for Automatic Ringing Linefeed Control External Bipolar Transistor Control SQH LFS[2:0] CBY ETBE ETBO[1:0] LCD[7:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OAT1[15:8] OIT1[7:0] OIT1[15:8] OAT2[7:0] OAT2[15:8] OIT2[7:0] OIT2[15:8] PAT[7:0]
45
PAT[15:8]
46
PIT[7:0]
47
PIT[15:8]
48 49 50 51 52
RAT[7:0] RAT[15:8] RIT[7:0] RIT[15:8] FSKDAT
64 65
LF[2:0] ETBA[1:0]
Preliminary Rev. 0.96
41
Si3230
Table 30. Direct Register Summary (Continued)
Register Name 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 92 93 Battery Feed Control Automatic/Manual Control Loop Closure/Ring Trip Detect Status Loop Closure Debounce Interval Ring Trip Detect Debounce Interval Loop Current Limit On-Hook Line Voltage Common Mode Voltage High Battery Voltage Low Battery Voltage Power Monitor Pointer Line Power Output Monitor Loop Voltage Sense Loop Current Sense TIP Voltage Sense RING Voltage Sense Battery Voltage Sense 1 Battery Voltage Sense 2 Transistor 1 Current Sense Transistor 2 Current Sense Transistor 3 Current Sense Transistor 4 Current Sense Transistor 5 Current Sense Transistor 6 Current Sense DC-DC Converter PWM Period DC-DC Converter Switching Delay DCCAL DCPOL LVSP LCSP VTIP[7:0] VRING[7:0] VBATS1[7:0] VBATS2[7:0] IQ1[7:0] IQ2[7:0] IQ3[7:0] IQ4[7:0] IQ5[7:0] IQ6[7:0] DCN[7:0] DCTOF[4:0] PWROM[7:0] LVS[5:0] LCS[5:0] VSGN VOC[5:0] VCM[5:0] VBATH[5:0] VBATL[5:0] PWRMP[2:0] MNCM MNDIF Bit 7 Bit 6 Bit 5 Bit 4 VOV SPDS Bit 3 FVBAT ABAT AORD DBIRAW LCDI[6:0] RTDI[6:0] ILIM[2:0] AOLD RTP Bit 2 Bit 1 Bit 0 TRACK AOPN LCR
42
Preliminary Rev. 0.96
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Table 30. Direct Register Summary (Continued)
Register Name 94 95 96 97 98 99 100 PWM Pulse Width Reserved Calibration Control/ Status Register 1 Calibration Control/ Status Register 2 RING Gain Mismatch Calibration Result TIP Gain Mismatch Calibration Result Differential Loop Current Gain Calibration Result Common Mode Loop Current Gain Calibration Result Current Limit Calibration Result Monitor ADC Offset Calibration Result Analog DAC/ADC Offset DAC Offset Calibration Result Common Mode Balance Calibration Result DC Peak Voltage Calibration Result Enhancement Enable ILIMEN FSKEN DCEN ZSEXT SWDB CALMG1[3:0] DACP DACOF[7:0] CMBAL[5:0] CMDCPK[3:0] LCVE DCFIL HYSTEN CAL CALSP CALR
CALM1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DCPW[7:0] CALT
CALM2
CALD
CALDAC
CALC
CALADC
CALIL
CALCM
CALGMR[R4:0] CALGMT[4:0] CALGD[4:0]
101
CALGC[4:0]
102 103 104 105 106 107 108
CALGIL[3:0] CALMG2[3:0] DACN ADCP ADCN
Preliminary Rev. 0.96
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Si3230
Register 0. SPI Mode Select Bit Name Type D7 SPIDC R/W D6 SPIM R/W D5 PNI[1:0] R D4 D3 D2 RNI[3:0] R D1 D0
Reset settings = 00xx_xxxx Bit 7 Name SPIDC SPI Daisy Chain Mode Enable. 0 = Disable SPI daisy chain mode. 1 = Enable SPI daisy chain mode. SPI Mode. 0 = Causes SDO to tri-state on rising edge of SCLK of LSB. 1 = Normal operation; SDO tri-states on rising edge of CS. Part Number Identification. 00 = Si3230 01 = Reserved 10 = Reserved 11 = Reserved Revision Number Identification. 0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc. Function
6
SPIM
5:4
PNI[1:0]
3:0
RNI[3:0]
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Register 9. Audio Gain Control Bit Name Type D7 RXHP R/W D6 TXHP R/W D5 TXM R/W D4 RXM R/W D3 ATX[1:0] R/W D2 D1 D0
ARX[1:0] R/W
Reset settings = 0000_0000 Bit 7 Name RXHP Function Receive Path High Pass Filter Disable. 0 = HPF enabled in receive path, RHDF. 1 = HPF bypassed in receive path, RHDF. Transmit Path High Pass Filter Disable. 0 = HPF enabled in transmit path, THPF. 1 = HPF bypassed in transmit path, THPF. Transmit Path Mute. Refer to position of digital mute in Figure 16 on page 35. 0 = Transmit signal passed. 1 = Transmit signal muted. Receive Path Mute. Refer to position of digital mute in Figure 16 on page 35. 0 = Receive signal passed. 1 = Receive signal muted. Analog Transmit Path Gain. 00 = 0 dB 01 = -3.5 dB 10 = 3.5 dB 11 = ATX gain = 0 dB; analog transmit path muted. Analog Receive Path Gain. 00 = 0 dB 01 = -3.5 dB 10 = 3.5 dB 11 = Analog receive path muted.
6
TXHP
5
TXM
4
RXM
3:2
ATX[1:0]
1:0
ARX[1:0]
Preliminary Rev. 0.96
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Si3230
Register 10. Two-Wire Impedance Synthesis Control Bit Name Type Reset settings = 0000_1000 Bit 7:6 5:4 Name Reserved CLC[1:0] Read returns zero. Line Capacitance Compensation. 00 = Off 01 = 4.7 nF 10 = 10 nF 11 = Reserved Two-Wire Impedance Synthesis Enable. 0 = Two-wire impedance synthesis disabled. 1 = Two-wire impedance synthesis enabled. Two-Wire Impedance Synthesis Selection. 000 = 600 001 = 900 010 = 600 + 2.16 F 011 = 900 + 2.16 F 100 = CTR21 (270 + 750 || 150 nF) 101 = Australia/New Zealand #1 (220 + 820 || 120 nF) 110 = Slovakia/Slovenia/South Africa (220 + 820 || 115 nF) 111 = New Zealand #2 (370 + 620 || 310 nF) Function D7 D6 D5 D4 D3 TISE R/W D2 D1 TISS[2:0] R/W D0
CLC[1:0] R/W
3
TISE
2:0
TISS[2:0]
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Preliminary Rev. 0.96
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Register 11. Hybrid Control Bit Name Type Reset settings = 0011_0011 Bit 7 6:4 Name Reserved HYBP[2:0] Read returns zero. Pulse Metering Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 = 0 dB 100 = -1.02 dB 101 = -1.94 dB 110 = -2.77 dB 111 = Off Read returns zero. Audio Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 = 0 dB 100 = -1.02 dB 101 = -1.94 dB 110 = -2.77 dB 111 = Off Function D7 D6 D5 HYBP[2:0] R/W D4 D3 D2 D1 HYBA[2:0] R/W D0
3 2:0
Reserved HYBA[2:0]
Preliminary Rev. 0.96
47
Si3230
Register 14. Power Down Control 1 Si3230 Bit Name Type Reset settings = 0001_0000 Si3211/Si3212 Bit Name Type Reset settings = 0001_0000 Bit 7:6 5 Name Reserved PMON Read returns zero. Pulse Metering DAC Power-On Control. 0 = Automatic power control. 1 = Override automatic control and force pulse metering DAC circuitry on. DC-DC Converter Power-Off Control (Si3230 only). 0 = Automatic power control. 1 = Override automatic control and force dc-dc circuitry off. Si3211/Si3212 = Read returns 1; it cannot be written. Monitor ADC Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force monitor ADC circuitry off. Read returns zero. DC Bias Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force dc bias circuitry off. SLIC Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force SLIC circuitry off. Function D7 D6 D5 PMON R/W D4 D3 MOF R/W D2 D1 BIASOF R/W D0 SLICOF R/W D7 D6 D5 PMON R/W D4 DCOF R/W D3 MOF R/W D2 D1 BIASOF R/W D0 SLICOF R/W
4
DCOF
3
MOF
2 1
Reserved BIASOF
0
SLICOF
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Preliminary Rev. 0.96
Si3230
Register 15. Power Down Control 2 Bit Name Type Reset settings = 0000_0000 Bit 7:6 5 Name Reserved ADCM Read returns zero. Analog to Digital Converter Manual/Automatic Power Control. 0 = Automatic power control. 1 = Manual power control; ADCON controls on/off state. Analog to Digital Converter On/Off Power Control. When ADCM = 1: 0 = Analog to digital converter powered off. 1 = Analog to digital converter powered on. ADCON has no effect when ADCM = 0. Digital to Analog Converter Manual/Automatic Power Control. 0 = Automatic power control. 1 = Manual power control; DACON controls on/off state. Digital to Analog Converter On/Off Power Control. When DACM = 1: 0 = Digital to analog converter powered off. 1 = Digital to analog converter powered on. DACON has no effect when DACM = 0. Transconductance Amplifier Manual/Automatic Power Control. 0 = Automatic power control. 1 = Manual power control; GMON controls on/off state. Transconductance Amplifier On/Off Power Control. When GMM = 1: 0 = Analog to digital converter powered off. 1 = Analog to digital converter powered on. GMON has no effect when GMM = 0. Function D7 D6 D5 ADCM R/W D4 ADCON R/W D3 DACM R/W D2 DACON R/W D1 GMM R/W D0 GMON R/W
4
ADCON
3
DACM
2
DACON
1
GMM
0
GMON
Preliminary Rev. 0.96
49
Si3230
Register 18. Interrupt Status 1 Bit Name Type D7 PMIP R/W D6 PMAP R/W D5 RGIP R/W D4 RGAP R/W D3 O2IP R/W D2 O2AP R/W D1 O1IP R/W D0 O1AP R/W
Reset settings = 0000_0000 Bit 7 Name PMIP Function Pulse Metering Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Pulse Metering Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Ringing Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Ringing Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Oscillator 2 Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Oscillator 2 Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Oscillator 1 Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Oscillator 1 Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending.
6
PMAP
5
RGIP
4
RGAP
3
O2IP
2
O2AP
1
O1IP
0
O1AP
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Preliminary Rev. 0.96
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Register 19. Interrupt Status 2 Bit Name Type D7 Q6AP R/W D6 Q5AP R/W D5 Q4AP R/W D4 Q3AP R/W D3 Q2AP R/W D2 Q1AP R/W D1 LCIP R/W D0 RTIP R/W
Reset settings = 0000_0000 Bit 7 Name Q6AP Function Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q5 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q4 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q3 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q2 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q1 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Loop Closure Transition Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Ring Trip Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending.
6
Q5AP
5
Q4AP
4
Q3AP
3
Q2AP
2
Q1AP
1
LCIP
0
RTIP
Preliminary Rev. 0.96
51
Si3230
Register 20. Interrupt Status 3 Si3230/Si3211 Bit Name Type Reset settings = 0000_0000 Si3212 Bit Name Type Reset settings = 0000_0000 Bit 7:3 2 Name Reserved CMCP Read returns zero. Common Mode Calibration Error Interrupt. This bit is set when off-hook/on-hook status changes during the common mode balance calibration. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Indirect Register Access Serviced Interrupt. This bit is set once a pending indirect register service request has been completed. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. DTMF Tone Detected Interrupt (Si3230 and Si3211 only). Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Si3212 = Reserved; read returns 0. Function D7 D6 D5 D4 D3 D2 CMCP R/W D1 INDP R/W D0 D7 D6 D5 D4 D3 D2 CMCP R/W D1 INDP R/W D0 DTMFP R/W
1
INDP
0
DTMFP
52
Preliminary Rev. 0.96
Si3230
Register 21. Interrupt Enable 1 Bit Name Type D7 PMIE R/W D6 PMAE R/W D5 RGIE R/W D4 RGAE R/W D3 O2IE R/W D2 O2AE R/W D1 O1IE R/W D0 O1AE R/W
Reset settings = 0000_0000 Bit 7 Name PMIE Function Pulse Metering Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Pulse Metering Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ringing Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ringing Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Oscillator 2 Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Oscillator 2 Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Oscillator 1 Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Oscillator 1 Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled.
6
PMAE
5
RGIE
4
RGAE
3
O2IE
2
O2AE
1
O1IE
0
O1AE
Preliminary Rev. 0.96
53
Si3230
Register 22. Interrupt Enable 2 Bit Name Type D7 Q6AE R/W D6 Q5AE R/W D5 Q4AE R/W D4 Q3AE R/W D3 Q2AE R/W D2 Q1AE R/W D1 LCIE R/W D0 RTIE R/W
Reset settings = 0000_0000 Bit 7 Name Q6AE Power Alarm Q6 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q5 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q4 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q3 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q2 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q1 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Loop Closure Transition Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ring Trip Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Function
6
Q5AE
5
Q4AE
4
Q3AE
3
Q2AE
2
Q1AE
1
LCIE
0
RTIE
54
Preliminary Rev. 0.96
Si3230
Register 23. Interrupt Enable 3 Bit Name Type Reset settings = 0000_0000 Bit 7:3 2 Name Reserved CMCE Read returns zero. Common Mode Calibration Error Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Indirect Register Access Serviced Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. DTMF Tone Detected Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Function D7 D6 D5 D4 D3 D2 CMCE R/W D1 INDE R/W D0 DTMFE R/W
1
INDE
0
DTMFE
Preliminary Rev. 0.96
55
Si3230
Register 24. DTMF Decode Status Bit Name Type Reset settings = 0000_0000 Bit 7:5 4 Name Reserved VAL Read returns zero. DTMF Valid Digit Decoded. 0 = Not currently detecting digit. 1 = Currently detecting digit. DTMF Digit. 0001 = "1" 0010 = "2" 0011 = "3" 0100 = "4" 0101 = "5" 0110 = "6" 0111 = "7" 1000 = "8" 1001 = "9" 1010 = "0" 1011 = "*" 1100 = "#" 1101 = "A" 1110 = "B" 1111 = "C" 0000 = "D" Function D7 D6 D5 D4 VAL R D3 D2 DIG[3:0] R D1 D0
3:0
DIG[3:0]
56
Preliminary Rev. 0.96
Si3230
Register 28. Indirect Data Access--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name IDA[7:0] Function Indirect Data Access--Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate--a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation). D7 D6 D5 D4 IDA[7:0] R/W D3 D2 D1 D0
Register 29. Indirect Data Access--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name IDA[15:8] Function Indirect Data Access--High Byte. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate--a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation). D7 D6 D5 D4 D3 D2 D1 D0
IDA[15:8] R/W
Preliminary Rev. 0.96
57
Si3230
Register 30. Indirect Address Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IAA[7:0] Function Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate--a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation). D7 D6 D5 D4 IAA[7:0] R/W D3 D2 D1 D0
Register 31. Indirect Address Status Bit Name Type Reset settings = 0000_0000 Bit 7:1 0 Name Reserved IAS Read returns zero. Indirect Access Status. 0 = No indirect memory access pending. 1 = Indirect memory access pending. Function D7 D6 D5 D4 D3 D2 D1 D0 IAS R
58
Preliminary Rev. 0.96
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Register 32. Oscillator 1 Control Bit Name Type D7 OSS1 R D6 REL R/W D5 OZ1 R/W D4 O1TAE R/W D3 O1TIE R/W D2 O1E R/W D1 D0
O1SO[1:0] R/W
Reset settings = 0000_0000 Bit 7 Name OSS1 Oscillator 1 Signal Status. 0 = Output signal inactive. 1 = Output signal active. Oscillator 1 Automatic Register Reload. This bit should be set for FSK signaling. 0 = Oscillator 1 will stop signaling after inactive timer expires. 1 = Oscillator 1 will continue to read register parameters and output signals. Oscillator 1 Zero Cross Enable. 0 = Signal terminates after active timer expires. 1 = Signal terminates at zero crossing after active timer expires. Oscillator 1 Active Timer Enable. 0 = Disable timer. 1 = Enable timer. Oscillator 1 Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. Oscillator 1 Enable. 0 = Disable oscillator. 1 = Enable oscillator. Oscillator 1 Signal Output Routing. 00 = Unassigned path (output not connected). 01 = Assign to transmit path. 10 = Assign to receive path. 11 = Assign to both paths. Function
6
REL
5
OZ1
4
O1TAE
3
O1TIE
2
O1E
1:0
O1SO[1:0]
Preliminary Rev. 0.96
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Si3230
Register 33. Oscillator 2 Control Bit Name Type D7 OSS2 R D6 D5 OZ2 R/W D4 O2TAE R/W D3 O2TIE R/W D2 O2E R/W D1 D0
O2SO[1:0] R/W
Reset settings = 0000_0000 Bit 7 Name OSS2 Oscillator 2 Signal Status. 0 = Output signal inactive. 1 = Output signal active. Read returns zero. Oscillator 2 Zero Cross Enable. 0 = Signal terminates after active timer expires. 1 = Signal terminates at zero crossing. Oscillator 2 Active Timer Enable. 0 = Disable timer. 1 = Enable timer. Oscillator 2 Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. Oscillator 2 Enable. 0 = Disable oscillator. 1 = Enable oscillator. Oscillator 2 Signal Output Routing. 00 = Unassigned path (output not connected) 01 = Assign to transmit path. 10 = Assign to receive path. 11 = Assign to both paths. Function
6 5
Reserved OZ2
4
O2TAE
3
O2TIE
2
O2E
1:0
O2SO[1:0]
60
Preliminary Rev. 0.96
Si3230
Register 34. Ringing Oscillator Control Bit Name Type D7 RSS R D6 D5 RDAC R D4 RTAE R/W D3 RTIE R/W D2 ROE R D1 RVO R/W D0 TSWS R/W
Reset settings = 0000_0000 Bit 7 Name RSS Function Ringing Signal Status. 0 = Ringing oscillator output signal inactive. 1 = Ringing oscillator output signal active. Read returns zero. Ringing Signal DAC/Linefeed Cross Indicator. For ringing signal start and stop, output to TIP and RING is suspended to ensure continuity with dc linefeed voltages. RDAC indicates that ringing signal is actually present at TIP and RING. 0 = Ringing signal not present at TIP and RING. 1 = Ringing signal present at TIP and RING. Ringing Active Timer Enable. 0 = Disable timer. 1 = Enable timer. Ringing Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. Ringing Oscillator Enable. 0 = Ringing oscillator disabled. 1 = Ringing oscillator enabled. Ringing Voltage Offset. 0 = No dc offset added to ringing signal. 1 = DC offset added to ringing signal. Trapezoid/Sinusoid Waveshape Select. 0 = Sinusoid 1 = Trapezoid
6 5
Reserved RDAC
4
RTAE
3
RTIE
2
ROE
1
RVO
0
TSWS
Preliminary Rev. 0.96
61
Si3230
Register 35. Pulse Metering Oscillator Control Bit Name Type D7 PSTAT R D6 D5 D4 PMAE R/W D3 PMIE R/W D2 PMOE R/W D1 D0
Reset settings = 0000_0000 Bit 7 Name PSTAT Pulse Metering Signal Status. 0 = Output signal inactive. 1 = Output signal active. Read returns zero. Pulse Metering Active Timer Enable. 0 = Disable timer. 1 = Enable timer. Pulse Metering Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. Pulse Metering Oscillator Enable. 0 = Disable oscillator. 1 = Enable oscillator. Read returns zero. Function
6:5 4
Reserved PMAE
3
PMIE
2
PMOE
1:0
Reserved
62
Preliminary Rev. 0.96
Si3230
Register 36. Oscillator 1 Active Timer--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OAT1[7:0] Oscillator 1 Active Timer. LSB = 125 s Function D7 D6 D5 D4 D3 D2 D1 D0
OAT1[7:0] R/W
Register 37. Oscillator 1 Active Timer--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OAT1[15:8] Oscillator 1 Active Timer. Function D7 D6 D5 D4 D3 D2 D1 D0
OAT1[15:8] R/W
Register 38. Oscillator 1 Inactive Timer--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OIT1[7:0] Oscillator 1 Inactive Timer. LSB = 125 s Function D7 D6 D5 D4 D3 D2 D1 D0
OIT1[7:0] R/W
Preliminary Rev. 0.96
63
Si3230
Register 39. Oscillator 1 Inactive Timer--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OIT1[15:8] Oscillator 1 Inactive Timer. Function D7 D6 D5 D4 D3 D2 D1 D0
OIT1[15:8] R/W
Register 40. Oscillator 2 Active Timer--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OAT2[7:0] Oscillator 2 Active Timer. LSB = 125 s Function D7 D6 D5 D4 D3 D2 D1 D0
OAT2[7:0] R/W
Register 41. Oscillator 2 Active Timer--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OAT2[15:8] Oscillator 2 Active Timer. Function D7 D6 D5 D4 D3 D2 D1 D0
OAT2[15:8] R/W
64
Preliminary Rev. 0.96
Si3230
Register 42. Oscillator 2 Inactive Timer--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OIT2[7:0] Oscillator 2 Inactive Timer. LSB = 125 s Function D7 D6 D5 D4 D3 D2 D1 D0
OIT2[7:0] R/W
Register 43. Oscillator 2 Inactive Timer--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OIT2[15:8] Oscillator 2 Inactive Timer. Function D7 D6 D5 D4 D3 D2 D1 D0
OIT2[15:8] R/W
Register 44. Pulse Metering Oscillator Active Timer--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name PAT[7:0] Pulse Metering Active Timer. LSB = 125 s Function D7 D6 D5 D4 PAT[7:0] R/W D3 D2 D1 D0
Preliminary Rev. 0.96
65
Si3230
Register 45. Pulse Metering Oscillator Active Timer--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name PAT[15:8] Pulse Metering Active Timer. Function D7 D6 D5 D4 D3 D2 D1 D0
PAT[15:8] R/W
Register 46. Pulse Metering Oscillator Inactive Timer--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name PIT[7:0] Pulse Metering Inactive Timer. LSB = 125 s Function D7 D6 D5 D4 PIT[7:0] R/W D3 D2 D1 D0
Register 47. Pulse Metering Oscillator Inactive Timer--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name PIT[15:8] Pulse Metering Inactive Timer. Function D7 D6 D5 D4 D3 D2 D1 D0
PIT[15:8] R/W
66
Preliminary Rev. 0.96
Si3230
Register 48. Ringing Oscillator Active Timer--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name RAT[7:0] Ringing Active Timer. LSB = 125 s Function D7 D6 D5 D4 RAT[7:0] R/W D3 D2 D1 D0
Register 49. Ringing Oscillator Active Timer--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name RAT[15:8] Ringing Active Timer. Function D7 D6 D5 D4 D3 D2 D1 D0
RAT[15:8] R/W
Register 50. Ringing Oscillator Inactive Timer--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name RIT[7:0] Ringing Inactive Timer. LSB = 125 s Function D7 D6 D5 D4 RIT[7:0] R/W D3 D2 D1 D0
Preliminary Rev. 0.96
67
Si3230
Register 51. Ringing Oscillator Inactive Timer--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name RIT[15:8] Ringing Inactive Timer. Function D7 D6 D5 D4 D3 D2 D1 D0
RIT[15:8] R/W
Register 52. FSK Data Bit Name Type Reset settings = 0000_0000 Bit 7:1 0 Name Reserved FSKDAT Read returns zero. FSK Data. When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6), this bit serves as the buffered input for FSK generation bit stream data. Function D7 D6 D5 D4 D3 D2 D1 D0 FSKDAT R/W
Register 63. Loop Closure Debounce Interval Bit Name Type Reset settings = 0011_0010 (revision C); 0101_0100 (subsequent revisions) Bit 7:0 Name LCD[7:0] Function Loop Closure Debounce Interval for Automatic Ringing. This register sets the loop closure debounce interval for the ringing silent period when using automatic ringing cadences. The value may be set between 0 ms (0x00) and 159 ms (0x7F) in 1.25 ms steps. D7 D6 D5 D4 D3 D2 D1 D0
LCD[7:0]
68
Preliminary Rev. 0.96
Si3230
Register 64. Linefeed Control Bit Name Type Reset settings = 0000_0000 Bit 7 6:4 Name Reserved LFS[2:0] Read returns zero. Linefeed Shadow. This register reflects the actual realtime linefeed state. Automatic operations may cause actual linefeed state to deviate from the state defined by linefeed register (e.g., when linefeed equals ringing state, LFS will equal on-hook transmission state during ringing silent period and ringing state during ring burst). 000 = Open 001 = Forward active 010 = Forward on-hook transmission 011 = TIP open 100 = Ringing 101 = Reverse active 110 = Reverse on-hook transmission 111 = RING open Read returns zero. Linefeed. Writing to this register sets the linefeed state. 000 = Open 001 = Forward active 010 = Forward on-hook transmission 011 = TIP open 100 = Ringing 101 = Reverse active 110 = Reverse on-hook transmission 111 = RING open Function D7 D6 D5 LFS[2:0] R D4 D3 D2 D1 LF[2:0] R/W D0
3 2:0
Reserved LF[2:0]
Preliminary Rev. 0.96
69
Si3230
Register 65. External Bipolar Transistor Control Bit Name Type D7 D6 SQH R/W D5 CBY R/W D4 ETBE R/W D3 D2 D1 D0
ETBO[1:0] R/W
ETBA[1:0] R/W
Reset settings = 0110_0001 Bit 7 6 Name Reserved SQH Read returns zero. Audio Squelch. 0 = No squelch. 1 = STIPAC and SRINGAC pins squelched. Capacitor Bypass. 0 = Capacitors CP (C1) and CM (C2) in circuit. 1 = Capacitors CP (C1) and CM (C2) bypassed. External Transistor Bias Enable. 0 = Bias disabled. 1 = Bias enabled. External Transistor Bias Levels--On-Hook Transmission State. DC bias current which flows through external BJTs in the on-hook transmission state. Increasing this value increases the compliance of the ac longitudinal balance circuit. 00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = Reserved External Transistor Bias Levels--Active Off-Hook State. DC bias current which flows through external BJTs in the active off-hook state. Increasing this value increases the compliance of the ac longitudinal balance circuit. 00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = Reserved Function
5
CBY
4
ETBE
3:2
ETBO[1:0]
1:0
ETBA[1:0]
70
Preliminary Rev. 0.96
Si3230
Register 66. Battery Feed Control Bit Name Type Reset settings = 0000_0011 Bit 7:5 4 Name Reserved VOV Read returns zero. Overhead Voltage Range Increase. This bit selects the programmable range for VOV, which is defined in indirect Register 41. 0 = VOV = 0 V to 9 V 1 = VOV = 0 V to 13.5 V VBAT Manual Setting. 0 = Normal operation 1 = VBAT tracks VBATH register. 2:1 0 Reserved TRACK Read returns zero. DC-DC Converter Tracking Mode. 0 = |VBAT| will not decrease below VBATL. 1 = VBAT tracks VRING. Function D7 D6 D5 D4 VOV R/W D3 FVBAT R/W D2 D1 D0 TRACK R/W
3
FVBAT
Preliminary Rev. 0.96
71
Si3230
Register 67. Automatic/Manual Control Bit Name Type D7 D6 MNCM R/W D5 MNDIF R/W D4 SPDS R/W D3 ABAT R/W D2 AORD R/W D1 AOLD R/W D0 AOPN R/W
Reset settings = 0001_1111 Bit 7 6 Name Reserved MNCM Read returns zero. Common Mode Manual/Automatic Select. 0 = Automatic control. 1 = Manual control, in which TIP (forward) or RING (reverse) forces voltage to follow VCM value. Differential Mode Manual/Automatic Select. 0 = Automatic control. 1 = Manual control (forces differential voltage to follow VOC value). Speed-Up Mode Enable. 0 = Speed-up disabled. 1 = Automatic speed-up. Battery Feed Automatic/Manual Select. 0 = Automatic mode disabled. 1 = Automatic mode enabled (automatic switching to low battery in off-hook state). Automatic/Manual Ring Trip Detect. 0 = Manual mode. 1 = Enter off-hook active state automatically upon ring trip detect. Automatic/Manual Loop Closure Detect. 0 = Manual mode. 1 = Enter off-hook active state automatically upon loop closure detect. Power Alarm Automatic/Manual Detect. 0 = Manual mode. 1 = Enter open state automatically upon power alarm. Function
5
MNDIF
4
SPDS
3
ABAT
2
AORD
1
AOLD
0
AOPN
72
Preliminary Rev. 0.96
Si3230
Register 68. Loop Closure/Ring Trip Detect Status Bit Name Type Reset settings = 0000_0000 Bit 7:3 2 Name Reserved DBIRAW Read returns zero. Ring Trip/Loop Closure Unfiltered Output. State of this bit reflects the realtime output of ring trip and loop closure detect circuits before debouncing. 0 = Ring trip/loop closure threshold exceeded. 1 = Ring trip/loop closure threshold not exceeded. Ring Trip Detect Indicator (Filtered Output). 0 = Ring trip detect has not occurred. 1 = Ring trip detect occurred. Loop Closure Detect Indicator (Filtered Output). 0 = Loop closure detect has not occurred. 1 = Loop closure detect has occurred. Function D7 D6 D5 D4 D3 D2 DBIRAW R D1 RTP R D0 LCR R
1
RTP
0
LCR
Register 69. Loop Closure Debounce Interval Bit Name Type Reset settings = 0000_1010 Bit 7 6:0 Name Reserved LCDI[6:0] Read returns zero. Loop Closure Debounce Interval. The value written to this register defines the minimum steady state debounce time. Value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12.5 ms. Function D7 D6 D5 D4 D3 LCDI[6:0] R/W D2 D1 D0
Preliminary Rev. 0.96
73
Si3230
Register 70. Ring Trip Detect Debounce Interval Bit Name Type Reset settings = 0000_1010 Bit 7 6:0 Name Reserved RTDI[6:0] Read returns zero. Ring Trip Detect Debounce Interval. The value written to this register defines the minimum steady state debounce time. The value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12.5 ms. Function D7 D6 D5 D4 D3 RTDI[6:0] R/W D2 D1 D0
Register 71. Loop Current Limit Bit Name Type Reset settings = 0000_0000 Bit 7:3 2:0 Name Reserved ILIM[2:0] Read returns zero. Loop Current Limit. The value written to this register sets the constant loop current. The value may be set between 20 mA (0x00) and 41 mA (0x07) in 3 mA steps. Function D7 D6 D5 D4 D3 D2 D1 ILIM[2:0] R/W D0
74
Preliminary Rev. 0.96
Si3230
Register 72. On-Hook Line Voltage Bit Name Type D7 D6 VSGN R/W D5 D4 D3 D2 D1 D0
VOC[5:0] R/W
Reset settings = 0010_0000 Bit 7 6 Name Reserved VSGN Read returns zero. On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage polarity (VTIP-VRING). 0 = VTIP-VRINGis positive 1 = VTIP-VRING is negative On-Hook Line Voltage. The value written to this register sets the on-hook line voltage (VTIP-VRING). Value may be set between 0 V (0x00) and 94.5 V (0x3F) in 1.5 V steps. Default value = 48 V. Function
5:0
VOC[5:0]
Register 73. Common Mode Voltage Bit Name Type Reset settings = 0000_0010 Bit 7:6 5:0 Name Reserved VCM[5:0] Read returns zero. Common Mode Voltage. The value written to this register sets VTIP for forward active and forward on-hook transmission states and VRING for reverse active and reverse on-hook transmission states. The value may be set between 0 V (0x00) and -94.5 V (0x3F) in 1.5 V steps. Default value = -3 V. Function D7 D6 D5 D4 D3 D2 D1 D0
VCM[5:0] R/W
Preliminary Rev. 0.96
75
Si3230
Register 74. High Battery Voltage Bit Name Type Reset settings = 0011_0010 Bit 7:6 5:0 Name Reserved VBATH[5:0] Read returns zero. High Battery Voltage. The value written to this register sets high battery voltage. VBATH must be greater than or equal to VBATL. The value may be set between 0 V (0x00) and -94.5 V (0x3F) in 1.5 V steps. Default value = -75 V. For Si3211 and Si3212, VBATH must be set equal to externally supplied VBATH input voltage. Function D7 D6 D5 D4 D3 D2 D1 D0
VBATH[5:0] R/W
Register 75. Low Battery Voltage Bit Name Type Reset settings = 0001_0000 Bit 7:6 5:0 Name Reserved VBATL[5:0] Read returns zero. Low Battery Voltage. The value written to this register sets low battery voltage. VBATH must be greater than or equal to VBATL. The value may be set between 0 V (0x00) and -94.5 V (0x3F) in 1.5 V steps. Default value = -24 V. For Si3211 and Si3212, VBATL must be set equal to externally supplied VBATL input voltage. Function D7 D6 D5 D4 D3 D2 D1 D0
VBATL[5:0] R/W
76
Preliminary Rev. 0.96
Si3230
Register 76. Power Monitor Pointer Bit Name Type Reset settings = 0000_0000 Bit 7:3 2:0 Name Reserved PWRMP[2:0] Read returns zero. Power Monitor Pointer. Selects the external transistor from which to read power output. The power of the selected transistor is read in the PWROM register. 000 = Q1 001 = Q2 010 = Q3 011 = Q4 100 = Q5 101 = Q6 110 = Undefined 111 = Undefined Function D7 D6 D5 D4 D3 D2 D1 PWRMP[2:0] R/W D0
Register 77. Line Power Output Monitor Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name PWROM[7:0] Function Line Power Output Monitor. This register reports the realtime power output of the transistor selected using PWRMP. The range is 0 W (0x00) to 7.8 W (0xFF) in 30.4 mW steps for Q1, Q2, Q5, and Q6. The range is 0 W (0x00) to 0.9 W (0xFF) in 3.62 mW steps for Q3 and Q4. D7 D6 D5 D4 D3 D2 D1 D0
PWROM[7:0] R
Preliminary Rev. 0.96
77
Si3230
Register 78. Loop Voltage Sense Bit Name Type D7 D6 LVSP R D5 D4 D3 LVS[5:0] R D2 D1 D0
Reset settings = 0000_0000 Bit 7 6 Name Reserved LVSP Read returns zero. Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage (VTIP - VRING). 0 = Positive loop voltage (VTIP > VRING). 1 = Negative loop voltage (VTIP < VRING). Loop Voltage Sense Magnitude. This register reports the magnitude of the differential loop voltage (VTIP-VRING). The range is 0 V to 94.5 V in 1.5 V steps. Function
5:0
LVS[5:0]
Register 79. Loop Current Sense Bit Name Type D7 D6 LCSP R D5 D4 D3 LCS[5:0] R D2 D1 D0
Reset settings = 0000_0000 Bit 7 6 Name Reserved LCSP Read returns zero. Loop Current Sense Polarity. This register reports the polarity of the loop current. 0 = Positive loop current (forward direction). 1 = Negative loop current (reverse direction). Loop Current Sense Magnitude. This register reports the magnitude of the loop current. The range is 0 mA to 78.75 mA in 1.25 mA steps. Function
5:0
LCS[5:0]
78
Preliminary Rev. 0.96
Si3230
Register 80. TIP Voltage Sense Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name VTIP[7:0] Function TIP Voltage Sense. This register reports the realtime voltage at TIP with respect to ground. The range is 0 V (0x00) to -95.88 V (0xFF) in .376 V steps. D7 D6 D5 D4 D3 D2 D1 D0
VTIP[7:0] R
Register 81. RING Voltage Sense Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name VRING[7:0] Function RING Voltage Sense. This register reports the realtime voltage at RING with respect to ground. The range is 0 V (0x00) to -95.88 V (0xFF) in .376 V steps. D7 D6 D5 D4 D3 D2 D1 D0
VRING[7:0] R
Register 82. Battery Voltage Sense 1 Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name VBATS1[7:0] Function Battery Voltage Sense 1. This register is one of two registers that reports the realtime voltage at VBAT with respect to ground. The range is 0 V (0x00) to -95.88 V (0xFF) in .376 V steps. D7 D6 D5 D4 D3 D2 D1 D0
VBATS1[7:0] R
Preliminary Rev. 0.96
79
Si3230
Register 83. Battery Voltage Sense 2 Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name VBATS2[7:0] Function Battery Voltage Sense 2. This register is one of two registers that reports the realtime voltage at VBAT with respect to ground. The range is 0 V (0x00) to -95.88 V (0xFF) in .376 V steps. D7 D6 D5 D4 D3 D2 D1 D0
VBATS2[7:0] R
Register 84. Transistor 1 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ1[7:0] Function Transistor 1 Current Sense. This register reports the realtime current through Q1. The range is 0 A (0x00) to 81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the additional ETBO/A current. D7 D6 D5 D4 IQ1[7:0] R D3 D2 D1 D0
Register 85. Transistor 2 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ2[7:0] Function Transistor 2 Current Sense. This register reports the realtime current through Q2. The range is 0 A (0x00) to 81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the additional ETBO/A current. D7 D6 D5 D4 IQ2[7:0] R D3 D2 D1 D0
80
Preliminary Rev. 0.96
Si3230
Register 86. Transistor 3 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ3[7:0] Function Transistor 3 Current Sense. This register reports the realtime current through Q3. The range is 0 A (0x00) to 9.59 mA (0xFF) in 37.6 A steps. D7 D6 D5 D4 IQ3[7:0] R D3 D2 D1 D0
Register 87. Transistor 4 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ4[7:0] Function Transistor 4 Current Sense. This register reports the realtime current through Q4. The range is 0 A (0x00) to 9.59 mA (0xFF) in 37.6 A steps. D7 D6 D5 D4 IQ4[7:0] R D3 D2 D1 D0
Register 88. Transistor 5 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ5[7:0] Function Transistor 5 Current Sense. This register reports the realtime current through Q5. The range is 0 A (0x00) to 80.58 mA (0xFF) in .316 mA steps. D7 D6 D5 D4 IQ5[7:0] R D3 D2 D1 D0
Preliminary Rev. 0.96
81
Si3230
Register 89. Transistor 6 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ6[7:0] Function Transistor 6 Current Sense. This register reports the realtime current through Q6. The range is 0 A (0x00) to 80.58 mA (0xFF) in .316 mA steps. D7 D6 D5 D4 IQ6[7:0] R D3 D2 D1 D0
Register 92. DC-DC Converter PWM Period Bit Name Type D7 DCN[7] R/W D6 1 R D5 D4 D3 D2 D1 D0
DCN[5:0] R/W
Reset settings = 1111_1111 Bit 7:0 Name DCN[7:0] Function DC-DC Converter Period. This bit sets the PWM period for the dc-dc converter. The range is 3.906 s (0x40) to 15.564 s (0xFF) in 61.035 ns steps. Bit 6 is fixed to one and read-only, so there are two ranges of operation: 3.906 s-7.751 s, used for MOSFET transistor switching. 11.719 s-15.564 s, used for BJT transistor switching.
82
Preliminary Rev. 0.96
Si3230
Register 93. DC-DC Converter Switching Delay Bit Name Type D7 DCCAL R/W D6 D5 DCPOL R D4 D3 D2 DCTOF[4:0] R/W D1 D0
Reset settings = 0001_0100 Bit 7 Name DCCAL Function DC-DC Converter Peak Current Monitor Calibration Status (Si3230 only). Writing a one to this bit starts the dc-dc converter peak current monitor calibration routine. 0 = Normal operation. 1 = Calibration being performed. Read returns zero. DC-DC Converter Feed Forward Pin (DCFF) Polarity. This read-only register bit indicates the polarity relationship of the DCFF pin to the DCDRV pin. Two versions of the Si3230 are offered to support the two relationships. 0 = DCFF pin polarity is opposite of DCDRV pin (Si3230). 1 = DCFF pin polarity is same as DCDRV pin (Si3230M). DC-DC Converter Minimum Off Time. This register sets the minimum off time for the pulse width modulated dc-dc converter control. TOFF = (DCTOF + 4) 61.035 ns.
6 5
Reserved DCPOL
4:0
DCTOF[4:0]
Preliminary Rev. 0.96
83
Si3230
Register 94. DC-DC Converter PWM Pulse Width Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name DCPW[7:0] Function DC-DC Converter Pulse Width. Pulse width of DCDRV is given by PW = (DCPW - DCTOF - 4) 61.035 ns. D7 D6 D5 D4 D3 D2 D1 D0
DCPW[7:0] R
84
Preliminary Rev. 0.96
Si3230
Register 96. Calibration Control/Status Register 1 Bit Name Type D7 D6 CAL R/W D5 CALSP R/W D4 CALR R/W D3 CALT R/W D2 CALD R/W D1 CALC R/W D0 CALIL R/W
Reset settings = 0001_1111 Bit 7 6 Name Reserved CAL Read returns zero. Calibration Control/Status Bit. Setting this bit begins calibration of the entire system. 0 = Normal operation or calibration complete. 1 = Calibration in progress. Calibration Speedup. Setting this bit shortens the time allotted for VBAT settling at the beginning of the calibration cycle. 0 = 300 ms 1 = 30 ms RING Gain Mismatch Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. TIP Gain Mismatch Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Differential DAC Gain Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Common Mode DAC Gain Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. ILIM Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Function
5
CALSP
4
CALR
3
CALT
2
CALD
1
CALC
0
CALIL
Preliminary Rev. 0.96
85
Si3230
Register 97. Calibration Control/Status Register 2 Bit Name Type Reset settings = 0001_1111 Bit 7:5 4 Name Reserved CALM1 Read returns zero. Monitor ADC Calibration 1. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Monitor ADC Calibration 2. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. DAC Calibration. Setting this bit begins calibration of the audio DAC offset. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. ADC Calibration. Setting this bit begins calibration of the audio ADC offset. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Common Mode Balance Calibration. Setting this bit begins calibration of the ac longitudinal balance. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Function D7 D6 D5 D4 CALM1 R/W D3 CALM2 R/W D2 CALDAC R/W D1 CALADC R/W D0 CALCM R/W
3
CALM2
2
CALDAC
1
CALADC
0
CALCM
86
Preliminary Rev. 0.96
Si3230
Register 98. RING Gain Mismatch Calibration Result Bit Name Type Reset settings = 0001_0000 Bit 7:5 4:0 Name Reserved CALGMR[4:0] Read returns zero. Gain Mismatch of IE Tracking Loop for RING Current. Function D7 D6 D5 D4 D3 D2 CALGMR[4:0] R/W D1 D0
Register 99. TIP Gain Mismatch Calibration Result Bit Name Type Reset settings = 0001_0000 Bit 7:5 4:0 Name Reserved CALGMT[4:0] Read returns zero. Gain Mismatch of IE Tracking Loop for TIP Current. Function D7 D6 D5 D4 D3 D2 CALGMT[4:0] R/W D1 D0
Register 100. Differential Loop Current Gain Calibration Result Bit Name Type Reset settings = 0001_0001 Bit 7:5 4:0 Name Reserved CALGD[4:0] Read returns zero. Differential DAC Gain Calibration Result. Function D7 D6 D5 D4 D3 D2 CALGD[4:0] R/W D1 D0
Preliminary Rev. 0.96
87
Si3230
Register 101. Common Mode Loop Current Gain Calibration Result Bit Name Type Reset settings = 0001_0001 Bit 7:5 4:0 Name Reserved CALGC[4:0] Read returns zero. Common Mode DAC Gain Calibration Result. Function D7 D6 D5 D4 D3 D2 CALGC[4:0] R/W D1 D0
Register 102. Current Limit Calibration Result Bit Name Type Reset settings = 0000_1000 Bit 7:5 3:0 Name Reserved CALGIL[3:0] Read returns zero. Current Limit Calibration Result. Function D7 D6 D5 D4 D3 D2 D1 D0
CALGIL[3:0] R/W
Register 103. Monitor ADC Offset Calibration Result Bit Name Type Reset settings = 1000_1000 Bit 7:4 3:0 Name CALMG1[3:0] CALMG2[3:0] Function Monitor ADC Offset Calibration Result 1. Monitor ADC Offset Calibration Result 2. D7 D6 D5 D4 D3 D2 D1 D0
CALMG1[3:0] R/W
CALMG2[3:0] R/W
88
Preliminary Rev. 0.96
Si3230
Register 104. Analog DAC/ADC Offset Bit Name Type Reset settings = 0000_0000 Bit 7:4 3 2 1 0 Name Reserved DACP DACN ADCP ADCN Read returns zero. Positive Analog DAC Offset. Negative Analog DAC Offset. Positive Analog ADC Offset. Negative Analog ADC Offset. Function D7 D6 D5 D4 D3 DACP R/W D2 DACN R/W D1 ADCP R/W D0 ADCN R/W
Register 105. DAC Offset Calibration Result Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name DACOF[7:0] DAC Offset Calibration Result. Function D7 D6 D5 D4 D3 D2 D1 D0
DACOF[7:0] R/W
Register 106. Common Mode Calibration Result Bit Name Type Reset settings = 0010_0000 Bit 7:6 5:0 Name Reserved CMBAL[5:0] Read returns zero. Common Mode Calibration Result. Function D7 D6 D5 D4 D3 D2 D1 D0
CMBAL[5:0]
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Register 107. DC Peak Current Monitor Calibration Result Bit Name Type Reset settings = 0000_1000 Bit 7:4 3:0 Name Reserved CMDCPK[3:0] Read returns zero. DC Peak Current Monitor Calibration Result. Function D7 D6 D5 D4 D3 D2 D1 D0
CMDCPK[3:0] R/W
Register 108. Enhancement Enable Bit Name Type D7 ILIMEN R/W D6 FSKEN R/W D5 DCSU R/W D4 ZSEXT R/W D3 D2 LCVE R/W D1 DCFIL R/W D0 HYSTEN R/W
Reset settings = 0000_0000 Bit 7 Name ILIMEN Function Current Limit Increase. When enabled, this bit temporarily increases the maximum differential current limit at the end of a ring burst to enable a faster settling time to a dc linefeed state. 0 = The value programmed in ILIM (direct Register 71) is used. 1 = The maximum differential loop current limit is temporarily increased to 41 mA. FSK Generation Enhancement. When enabled, this bit will increase the clocking rate of tone generator 1 to 24 kHz only when the REL bit (direct Register 32, bit 6) is set. Also, dedicated oscillator registers are used for FSK generation (indirect registers 99-104). Audio tones are generated using this new higher frequency, and oscillator 1 active and inactive timers have a finer bit resolution of 41.67 s. This provides greater resolution during FSK caller ID signal generation. 0 = Tone generator always clocked at 8 kHz; OSC1, OSC1X., and OSC1Y are always used. 1 = Tone generator module clocked at 24 kHz and dedicated FSK registers used only when REL = 1; otherwise clocked at 8 kHz. DC-DC Converter Control Speedup. When enabled, this bit invokes a multi-threshold error control algorithm which allows the dc-dc converter to adjust more quickly to voltage changes. 0 = Normal control algorithm used. 1 = Multi-threshold error control algorithm used.
6
FSKEN
5
DCSU
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Bit 4 Name ZSEXT Function Impedance Internal Reference Resistor Disable. When enabled, this bit removes the internal reference resistor used to synthesize ac impedances for 600 + 2.1 F and 900 + 2.16 F so that an external resistor reference may be used. 0 = Internal resistor used to generate 600 + 2.1 F and 900 + 2.16 F impedances. 1 = Internal resistor removed from circuit. Battery Switch Debounce. When enabled, this bit allows debouncing of the battery switching circuit only when transitioning from VBATH to VBATL external battery supplies (EXTBAT = 1). 0 = No debounce used. 1 = 60 ms debounce period used. Voltage-Based Loop Closure. Enables loop closure to be determined by the TIP-to-RING voltage rather than loop current. 0 = Loop closure determined by loop current. 1 = Loop closure determined by TIP-to-RING voltage. DC-DC Converter Squelch. When enabled, this bit squelches noise in the audio band from the dc-dc converter control loop. 0 = Voice band squelch disabled. 1 = Voice band squelch enabled. Loop Closure Hysteresis Enable. When enabled, this bit allows hysteresis to the loop closure calculation. The upper and lower hysteresis thresholds are defined by indirect registers 28 and 43, respectively. 0 = Loop closure hysteresis disabled. 1 = Loop closure hysteresis enabled.
3
SWDB
2
LCVE
1
DCFIL
0
HYSTEN
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4. Indirect Registers
Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. In this case, the contents of IDA are written to indirect memory at the location referenced by IAA at the next indirect register update. A write to IAA without first writing to IDA is interpreted as a read request from an indirect register. In this case, the value located at IAA is written to IDA at the next indirect register update. Indirect registers are updated at a rate of 16 kHz. For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition an interrupt, IND (Register 20), can be generated upon completion of the indirect transfer.
4.1. DTMF Decoding
All values are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state.
Table 31. DTMF Indirect Registers Summary
Addr. D15 0 1 2 3 4 5 6 7 8 9 10 11 12 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ROW0[15:0] ROW1[15:0] ROW2[15:0] ROW3[15:0] COL[15:0] FWDTW[15:0] REVTW[15:0] ROWREL[15:0] COLREL[15:0] ROW2[15:0] COL2[15:0] PWRMIN[15:0] HOTL[15:0]
Table 32. DTMF Indirect Registers Description
Addr. 0 Description DTMF Row 0 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 0 DTMF detection. If the ratio of power in row 0 to total power in the row band is greater than ROW0, then a row 0 signal is detected. A value of 0x7FF0 corresponds to a 1.0 ratio. DTMF Row 1 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 1 DTMF detection. If the ratio of power in row 1 to total power in the row band is greater than ROW1, then a row 1 signal is detected. A value of 0x7FF0 corresponds to a 1.0 ratio. Reference Page 34
1
34
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Table 32. DTMF Indirect Registers Description (Continued)
Addr. 2 Description DTMF Row 2 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 2 DTMF detection. If the ratio of power in row 2 to total power in the row band is greater than ROW2, then a row 2 signal is detected. A value of 0x7FF0 corresponds to a 1.0 ratio. DTMF Row 3 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 3 DTMF detection. If the ratio of power in row 3 to total power in the row band is greater than ROW3, then a row 3 signal is detected. A value of 0x7FF0 corresponds to a 1.0 ratio. DTMF Column Peak Magnitude Pass Threshold. This register sets the minimum power ratio threshold for column DTMF detection; all columns use the same threshold. If the ratio of power in a particular column to total power in the column band is greater than COL, then a column detect for that particular column signal is detected. A value of 0x7FF0 corresponds to a 1.0 ratio. DTMF Forward Twist Threshold. This register sets the threshold for the power ratio of row power to column power. A value of 0x7F0 corresponds to a 1.0 ratio. DTMF Reverse Twist Threshold. This register sets the threshold for the power ratio of column power to row power. A value of 0x7F0 corresponds to a 1.0 ratio. DTMF Row Ratio Threshold. This register sets the threshold for the power ratio of highest power row to the other rows. A value of 0x7F0 corresponds to a 1.0 ratio. DTMF Column Ratio Threshold. This register sets the threshold for the power ratio of highest power column to the other columns. A value of 0x7F0 corresponds to a 1.0 ratio. DTMF Row Second Harmonic Threshold. This register sets the threshold for the power ratio of peak row tone to its second harmonic. A value of 0x7F0 corresponds to a 1.0 ratio. DTMF Column Second Harmonic Threshold. This register sets the threshold for the power ratio of peak column tone to its second harmonic. A value of 0x7F0 corresponds to a 1.0 ratio. DTMF Power Minimum Threshold. This register sets the threshold for the minimum total power in the DTMF calculation, under which the calculation is ignored. DTMF Hot Limit Threshold. This register sets the two-step AGC in the DTMF path. Reference Page 34
3
34
4
34
5
34
6
34
7
34
8
34
9
34
10
34
11
34
12
34
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4.2. Oscillators
See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing register values. All values are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes.
Table 33. Oscillator Indirect Registers Summary
Addr. D15 13 14 15 16 17 18 19 20 21 22 23 24 25 ROFF[5:0] RCO[15:0] RNGX[15:0] RNGY[15:0] PLSD[15:0] PLSX[15:0] PLSCO[15:0] D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 OSC1[15:0] OSC1X[15:0] OSC1Y[15:0] OSC2[15:0] OSC2X[15:0] OSC2Y[15:0]
Table 34. Oscillator Indirect Registers Description
Addr. 13 14 15 16 17 18 19 Oscillator 1 Frequency Coefficient. Sets tone generator 1 frequency. Oscillator 1 Amplitude Register. Sets tone generator 1 signal amplitude. Oscillator 1 Initial Phase Register. Sets initial phase of tone generator 1 signal. Oscillator 2 Frequency Coefficient. Sets tone generator 2 frequency. Oscillator 2 Amplitude Register. Sets tone generator 2 signal amplitude. Oscillator 2 Initial Phase Register. Sets initial phase of tone generator 2 signal. Ringing Oscillator DC Offset. Sets dc offset component (VTIP-VRING) to ringing waveform. The range is 0 to 94.5 V in 1.5 V increments. Description Reference Page 27 27 27 27 27 27 29
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Table 34. Oscillator Indirect Registers Description (Continued)
Addr. 20 21 22 23 24 25 Description Ringing Oscillator Frequency Coefficient. Sets ringing generator frequency. Ringing Oscillator Amplitude Register. Sets ringing generator signal amplitude. Ringing Oscillator Initial Phase Register. Sets initial phase of ringing generator signal. Pulse Metering Oscillator Attack/Decay Ramp Rate. Sets pulse metering attack/decay ramp rate. Pulse Metering Oscillator Amplitude Register. Sets pulse metering generator signal amplitude. Pulse Metering Oscillator Frequency Coefficient. Sets pulse metering generator frequency. Reference Page 29 29 29 33 33 33
4.3. Digital Programmable Gain/Attenuation
See functional description sections of digital programmable gain/attenuation for guidelines on computing register values. All values are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes.
Table 35. Digital Programmable Gain/Attenuation Indirect Registers Summary
Addr. D15 26 27 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DACG[11:0] ADCG[11:0]
Table 36. Digital Programmable Gain/Attenuation Indirect Registers Description
Addr. 26 Description Receive Path Digital to Analog Converter Gain/Attenuation. This register sets gain/attenuation for the receive path. The digitized signal is effectively multiplied by DACG to achieve gain/attenuation. A value of 0x00 corresponds to - dB gain (mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain of 6 dB. Transmit Path Analog to Digital Converter Gain/Attenuation. This register sets gain/attenuation for the transmit path. The digitized signal is effectively multiplied by ADCG to achieve gain/attenuation. A value of 0x00 corresponds to - dB gain (mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain of 6 dB.
27
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Si3230
4.4. SLIC Control
See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes.
Table 37. SLIC Control Indirect Registers Summary
Addr. D15 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
*Note: Si3230 only.
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LCRT[5:0] RPTP[5:0] CML[5:0] CMH[5:0] PPT12[7:0] PPT34[7:0] PPT56[7:0] NCLR[12:0] NRTP[12:0] NQ12[12:0] NQ34[12:0] NQ56[12:0] VCMR[3:0] VMIND[3:0]* LCRTL[5:0]
Table 38. SLIC Control Indirect Registers Description
Addr. 28 Description Loop Closure Threshold. Loop closure detection threshold. This register defines the upper bounds threshold if hysteresis is enabled (direct Register 108, bit 0). The range is 0-80 mA in 1.27 mA steps. See "2.1.6. Loop Closure Detection" on page 22. Ring Trip Threshold. Ring trip detection threshold during ringing. See "2.4.6. Ring Trip Detection" on page 31. Common Mode Minimum Threshold for Speed-Up. This register defines the negative common mode voltage threshold. Exceeding this threshold enables a wider bandwidth of dc linefeed control for faster settling times. The range is 0-23.625 V in 0.375 V steps.
29 30
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Table 38. SLIC Control Indirect Registers Description (Continued)
Addr. 31 Description Common Mode Maximum Threshold for Speed-Up. This register defines the positive common mode voltage threshold. Exceeding this threshold enables a wider bandwidth of dc linefeed control for faster settling times. The range is 0-23.625 V in 0.375 V steps. Power Alarm Threshold for Transistors Q1 and Q2. Power Alarm Threshold for Transistors Q3 and Q4. Power Alarm Threshold for Transistors Q5 and Q6. Loop Closure Filter Coefficient. Ring Trip Filter Coefficient. Thermal Low Pass Filter Pole for Transistors Q1 and Q2. Thermal Low Pass Filter Pole for Transistors Q3 and Q4. Thermal Low Pass Filter Pole for Transistors Q5 and Q6. Common Mode Bias Adjust During Ringing. Recommended value of 0 decimal. DC-DC Converter VOV Voltage (Si3230 only). This register sets the overhead voltage, VOV, to be supplied by the dc-dc converter. When the VOV bit = 0 (direct Register 66, bit 4), VOV should be set between 0 and 9 V (VMIND = 0 to 6h). When the VOV bit = 1, VOV should be set between 0 and 13.5 V (VMIND = 0 to 9h). 42 43 Reserved. Loop Closure Threshold--Lower Bound. This register defines the lower threshold for loop closure hysteresis, which is enabled in bit 0 of direct Register 108. The range is 0-80 mA in 1.27 mA steps.
32 33 34 35 36 37 38 39 40 41
4.5. FSK Control
For detailed instructions on FSK signal generation, refer to "Application Note 32: FSK Generation" (AN32). These registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6).
Table 39. FSK Control Indirect Registers Summary
Addr. D15 99 100 101 102 103 104 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FSK0X[15:0] FSK0[15:0] FSK1X[15:0] FSK1[15:0] FSK01[15:0] FSK10[15:0]
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Table 40. FSK Control Indirect Registers Description
Addr. 99 Description FSK Amplitude Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when generating a space or "0". When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1X. FSK Frequency Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the frequency to be used when generating a space or "0". When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1. FSK Amplitude Coefficient for Mark. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when generating a mark or "1". When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1X. FSK Frequency Coefficient for Mark. When FSKEN = 1 and REL = 1, this register sets the frequency to be used when generating a mark or "1". When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1. FSK Transition Parameter from 0 to 1. When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is applied to signal amplitude when transitioning from a space (0) to a mark (1). FSK Transition Parameter from 1 to 0. When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is applied to signal amplitude when transitioning from a mark (1) to a space (0). Reference Page 29 and AN32
100
29 and AN32
101
29 and AN32
102
29 and AN32
103
29 and AN32
104
29 and AN32
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5. Pin Descriptions: Si3230
QFN
TEST2 PCLK INT CS SCLK SDI SDO
CS INT PCLK TEST2 NC FSYNC RESET SDCH SDCL VDDA1 IREF CAPP QGND CAPM STIPDC SRINGDC STIPE SVBAT SRINGE
TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
SCLK SDI SDO SDITHRU DCDRV DCFF TEST1 GNDD VDDD ITIPN ITIPP VDDA2 IRINGP IRINGN IGMP GNDA IGMN SRINGAC STIPAC
NC FSYNC RESET SDCH SDCL VDDA1 IREF CAPP QGND CAPM STIPDC SRINGDC
1 38 37 36 35 34 33 32 31 2 3 4 5 6 7 8 9 10 11 30 29 28 27 26 25 24 23 22 21
12 13 14 15 16 17 18 19 20
SDITHRU DCDRV DCFF TEST1 GNDD VDDD ITIPN ITIPP VDDA2 IRINGP IRINGN IGMP
Pin # QFN 35
Pin # TSSOP 1
Name CS
STIPE SVBAT SRINGE STIPAC SRINGAC IGMN GNDA
Description Chip Select. Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance. When active, the serial port is operational. Interrupt. Maskable interrupt output. Open drain output for wire-ORed operation. PCM Bus Clock. Clock input. Test. Enables test modes for Silicon Labs internal testing. This pin should always be tied to ground for normal operation.
36 37 38
2 3 4
INT PCLK TEST2
1 2
5 6
NC FSYNC
No Connect. Frame Synch. 8 kHz frame synchronization signal for the PCM bus. May be short or long pulse format.
3
7
RESET
Reset. Active low input. Hardware reset used to place all control registers in the default state.
4
8
SDCH
DC Monitor. DC-DC converter monitor input used to detect overcurrent situations in the converter.
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Si3230
Pin # QFN 5 Pin # TSSOP 9 Name SDCL DC Monitor. DC-DC converter monitor input used to detect overcurrent situations in the converter. 6 7 10 11 VDDA1 IREF Analog Supply Voltage. Analog power supply for internal analog circuitry. Current Reference. Connects to an external resistor used to provide a high accuracy reference current. 8 9 10 11 12 13 14 12 13 14 15 16 17 18 CAPP QGND CAPM STIPDC SLIC Stabilization Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback loops. Component Reference Ground. SLIC Stabilization Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback loops. TIP Sense. Analog current input used to sense voltage on the TIP lead. SRINGDC RING Sense. Analog current input used to sense voltage on the RING lead. STIPE SVBAT TIP Emitter Sense. Analog current input used to sense voltage on the Q6 emitter lead. VBAT Sense. Analog current input used to sense voltage on dc-dc converter output voltage lead. 15 16 17 18 19 20 21 22 19 20 21 22 23 24 25 26 SRINGE RING Emitter Sense. Analog current input used to sense voltage on the Q5 emitter lead. STIPAC TIP Transmit Input. Analog ac input used to detect voltage on the TIP lead. SRINGAC RING Transmit Input. Analog ac input used to detect voltage on the RING lead. IGMN GNDA IGMP IRINGN IRINGP Transconductance Amplifier External Resistor. Negative connection for transconductance gain setting resistor. Analog Ground. Ground connection for internal analog circuitry. Transconductance Amplifier External Resistor. Positive connection for transconductance gain setting resistor. Negative Ring Current Control. Analog current output driving Q3. Positive Ring Current Control. Analog current output driving Q2. Description
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Pin # QFN 23 24 25 26 27 28 Pin # TSSOP 27 28 29 30 31 32 Name VDDA2 ITIPP ITIPN VDDD GNDD TEST1 Analog Supply Voltage. Analog power supply for internal analog circuitry. Positive TIP Current Control. Analog current output driving Q1. Negative TIP Current Control. Analog current output driving Q4. Digital Supply Voltage. Digital power supply for internal digital circuitry. Digital Ground. Ground connection for internal digital circuitry. Test. Enables test modes for Silicon Labs internal testing. This pin should always be tied to ground for normal operation. 29 33 DCFF DC Feed-Forward/High Current General Purpose Output. Feed-forward drive of external bipolar transistors to improve dc-dc converter efficiency. 30 34 DCDRV DC Drive/Battery Switch. DC-DC converter control signal output which drives external bipolar transistor. Battery switch control signal output which drives external bipolar transistor. 31 32 33 34 35 36 37 38 SDITHRU SDI Passthrough. Cascaded SDI output signal for daisy-chain mode. SDO SDI SCLK Serial Port Data Out. Serial port control data output. Serial Port Data In. Serial port control data input. Serial Port Bit Clock Input. Serial port clock input. Controls the serial data on SDO and latches the data on SDI. Description
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6. Pin Descriptions: Si3201
TIP NC RING VBAT VBATH NC GND VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ITIPP ITIPN IRINGP IRINGN NC STIPE SRINGE NC
Pin # 1 2, 6, 9, 12 3 4 5 7 8 10 11 13 14 15 16
Name TIP NC RING VBAT VBATH GND VDD SRINGE STIPE IRINGN IRINGP ITIPN ITIPP
Input/ Output I/O -- I/O -- -- -- -- O O I I I I --
Description TIP Output--Connect to the TIP lead of the subscriber loop. No Internal Connection--Do not connect to any electrical signal. RING Output--Connect to the RING lead of the subscriber loop. Operating Battery Voltage--Connect to the battery supply. High Battery Voltage--This pin is internally connected to VBAT. Ground--Connect to a low impedance ground plane. Supply Voltage--Main power supply for all internal circuitry. Connect to a 3.3 V or 5 V supply. Decouple locally with a 0.1 F/6 V capacitor. RING Emitter Sense Output--Connect to the SRINGE pin of the Si321x pin. TIP Emitter Sense Output--Connect to the STIPE pin of the Si321x pin. Negative RING Current Control--Connect to the IRINGN lead of the Si321x. Positive RING Current Drive--Connect to the IRINGP lead of the Si321x. Negative TIP Current Control--Connect to the ITIPN lead of the Si321x. Positive TIP Current Control--Connect to the ITIPP lead of the Si321x. Exposed Thermal Pad--Connect to the bulk ground plane.
Bottom-Side Exposed Pad
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Preliminary Rev. 0.96
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7. Ordering Guide1,2
Device Si3230-X-FM Si3230-X-GM Si3230M-X-FM Si3230M-X-GM Si3230-KT Si3230-GT Si3230M-KT Si3230M-GT SI3201-FS Si3201-GS Si3201-KS Si3201-BS Description ProSLIC ProSLIC ProSLIC ProSLIC ProSLIC ProSLIC ProSLIC ProSLIC Line Interface Line Interface Line Interface Line Interface DCFF Pin Output DCDRV DCDRV DCDRV DCDRV DCDRV DCDRV DCDRV DCDRV n/a n/a n/a n/a Package QFN-38 QFN-38 QFN-38 QFN-38 TSSOP-38 TSSOP-38 TSSOP-38 TSSOP-38 SOIC-16 SOIC-16 SOIC-16 SOIC-16 Lead-Free and RoHS-Compliant Yes Yes Yes Yes No No No No Yes Yes No No Temp Range 0 to 70 C -40 to 85 C 0 to 70 C -40 to 85 C 0 to 70 C -40 to 85 C 0 to 70 C -40 to 85 C 0 to 70 C -40 to 85 C 0 to 70 C -40 to 85 C
Notes: 1. "X" denotes product revision. 2. Add an "R" at the end of the device to denote tape and reel options; 2500 quantity per reel.
Item Si3230PPQX-EVB Si3230PPQ1-EVB Si3230MPPQX-EVB Si3230MPPQ1-EVB Si3230DCQX-EVB Si3230DCQ1-EVB
Supported ProSLIC Si3230-QFN Si3230-QFN Si3230M-QFN Si3230M-QFN Si3230-QFN Si3230-QFN
Description Eval Board, Daughter Card Eval Board, Daughter Card Eval Board, Daughter Card Eval Board, Daughter Card Daughter Card Only Daughter Card Only
Linefeed Interface Discrete Si3201 Discrete Si3201 Discrete Si3201
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8. Package Outline: 38-Pin QFN
Figure 20 illustrates the package details for the Si3230. Table 41 lists the values for the dimensions shown in the illustration.
Figure 20. 38-Pin Quad Flat No-Lead Package (QFN)
Table 41. Package Diagram Dimensions1,2,3
Millimeters Symbol A A1 b D D2 e E E2 L L1 aaa bbb ccc ddd 5.10 0.35 0.03 -- -- -- -- 3.10 Min 0.75 0.00 0.18 Nom 0.85 0.01 0.23 5.00 BSC. 3.20 0.50 BSC. 7.00 BSC. 5.20 0.45 0.05 -- -- -- -- 5.30 0.55 0.08 0.10 0.10 0.08 0.10 3.30 Max 0.95 0.05 0.30
Notes: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. The drawing conforms to the JEDEC Solid State Outline MO-220, Variation VHKD-1. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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Preliminary Rev. 0.96
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9. Package Outline: 38-Pin TSSOP
Figure 21 illustrates the package details for the Si3230. Table 42 lists the values for the dimensions shown in the illustration.
B
2x E/2
E1
E L
ddd C B A
2x A D
aaa C
e
ccc
A Seating Plane C 38x
bbb
M
b
CBA
A1 Approximate device weight is 115.7 mg
C
Figure 21. 38-Pin Thin Shrink Small Outline Package (TSSOP) Table 42. Package Diagram Dimensions
Millimeters Symbol A A1 b B c D E e E1 L aaa bbb ccc ddd 4.30 0.45 0 0.09 9.60 -- 9.70 6.40 BSC 0.50 BSC 4.40 0.60 -- 0.10 0.08 0.05 0.20 4.50 0.75 8 0.20 9.80 Min -- 0.05 0.17 Nom -- -- -- Max 1.20 0.15 0.27
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10. Package Outline: 16-Pin SOIC
Figure 22 illustrates the package details for the Si3201. Table 43 lists the values for the dimensions shown in the illustration.
16
9 h E H -B- .25 M B M x45
1
B
8
Bottom Side Exposed Pad 2.3 x 3.6 mm
L Detail F
.25 M C A M B S
-A-
D C -C- A See Detail F
e
A1
Seating Plane
Weight: Approximate device weight is 0.15 grams.
Figure 22. 16-pin Small Outline Integrated Circuit (SOIC) Package Table 43. Package Diagram Dimensions
Millimeters Symbol A A1 B C D E e H h L Min 1.35 0 .33 .19 9.80 3.80 5.80 .25 .40 -- 0 Max 1.75 0.15 .51 .25 10.00 4.00 6.20 .50 1.27 0.10 8
1.27 BSC
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DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.9
Updated Table 1 on page 4.
Added QFN thermal resistance
Updated Table 10 on page 11.
Added Delay Time between Chip Selects, tcs, for continuous SCLK.
Updated Table 38 on page 96.
Recommended value for indirect register 40 changed from 6 to 0.
Updated Figure 3 on page 12.
C18, C19 changed from 1.0 F to 4.7 F.
Updated Figure 4 on page 13.
C10 changed from 22 nF to 0.1 F.
Updated "5. Pin Descriptions: Si3230" on page 99.
Added QFN pin description.
Updated "7. Ordering Guide1,2" on page 103. Added "8. Package Outline: 38-Pin QFN" on page 104. Updated "10. Package Outline: 16-Pin SOIC" on page 106.
Corrected dimension A1.
Revision 0.9 to Revision 0.95
Updated Figure 6 on page 15.
Moved ground line on R10 from base of Q1 to base of Q4 Moved ground line on R11 from base of Q2 to base of Q3.
Revision 0.95 to Revision 0.96
Added new Figure 5 on page 14.
Application schematic and BOM for MOSFET/ transformer DC-DC converter.
Added "2.2.3. MOSFET/Transformer Circuit Option Using Si3230M" on page 23.
Description for MOSFET/transformer DC-DC converter.
Updated "7. Ordering Guide" on page 103.
Removed "-BT" and "-FT" products.
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CONTACT INFORMATION
Silicon Laboratories Inc.
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The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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